Journal Articles
L. Groth,
A. Neskovic,
R. Buchty,
M. Berekovic, and
S. Mulhem
Compatibility Ratio as a Guideline for Hardware/DNN Co-Design of Embedded Accelerators
ACM Transactions on Embedded Computing Systems, ACM, 2026, 2,026
URL, DOI, RIS, BibTex
Compatibility Ratio as a Guideline for Hardware/DNN Co-Design of Embedded Accelerators
ACM Transactions on Embedded Computing Systems, ACM, 2026, 2,026
URL, DOI, RIS, BibTex
D. Najork,
A. Neskovic,
H. Lin,
C. Ewert,
S. Dreier,
M. Berekovic,
R. Buchty, and
M. S.
Single engine architecture for hardware root of trust
Journal of Cryptographic Engineering, Springer, 2025, 2,025
URL, DOI, RIS, BibTex
Single engine architecture for hardware root of trust
Journal of Cryptographic Engineering, Springer, 2025, 2,025
URL, DOI, RIS, BibTex
A. Nechi,
Z. Narjis,
R. Buchty,
M. Berekovic, and
S. Mulhem
Fast Reinforcement Learning for Robust Beam Codebooks in Future Communication Systems
IEEE Transactions on Communications, IEEE, 2025, 2,025
URL, RIS, BibTex
Fast Reinforcement Learning for Robust Beam Codebooks in Future Communication Systems
IEEE Transactions on Communications, IEEE, 2025, 2,025
URL, RIS, BibTex
A. Neskovic,
A. Kabour,
M. Eltantawi,
M. Berekovic,
R. Meyer, and
S. Mulhem
SCA-WAL: An Open-Source Framework for Power Side Channel Assessment at RTL and Netlist Level
IEEE Embedded Systems Letters, 2025, 2,025
URL, RIS, BibTex
SCA-WAL: An Open-Source Framework for Power Side Channel Assessment at RTL and Netlist Level
IEEE Embedded Systems Letters, 2025, 2,025
URL, RIS, BibTex
S. Mulhem,
E. Schultz,
L. Groth,
M. Berekovic, and
R. Buchty
Optimizing Systolic Array-Based NTT Accelerators
IEEE Embedded Systems Letters, IEEE, 2025, 2,025
URL, DOI, RIS, BibTex
Optimizing Systolic Array-Based NTT Accelerators
IEEE Embedded Systems Letters, IEEE, 2025, 2,025
URL, DOI, RIS, BibTex
A. Mahmoudi,
A. Neskovic,
C. Thermann,
R. Sehm,
C. Hübner,
T. Plattenteich,
R. Meyer,
R. Buchty,
et al.
A Systematic Mapping Study on SystemC/TLM Modeling Capabilities in New Research Domains
ACM Transactions on Design Automation of Electronic Systems, ACM, 2025, 2,025
URL, DOI, RIS, BibTex
A Systematic Mapping Study on SystemC/TLM Modeling Capabilities in New Research Domains
ACM Transactions on Design Automation of Electronic Systems, ACM, 2025, 2,025
URL, DOI, RIS, BibTex
C. Ewert,
A. Neskovic,
C. Heinz,
F. Muuss,
A. Treff,
M. Gourjon,
R. Buchty,
T. Eisenbarth,
et al.
Lightweight Authenticated Integration and In-Field Secure Operation of System-in-Package
ACM Transactions on Design Automation of Electronic Systems, 2025, 2,025
URL, DOI, RIS, BibTex
Lightweight Authenticated Integration and In-Field Secure Operation of System-in-Package
ACM Transactions on Design Automation of Electronic Systems, 2025, 2,025
URL, DOI, RIS, BibTex
J. Bouhlila and
M. Berekovic
When Simpler Models Win: The Limits of Parameter Sharing Neural Networks in Cross Technology SRAM Analysis
2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME), IEEE, Taormina, Italy 2025, 2,025
URL, RIS, BibTex
When Simpler Models Win: The Limits of Parameter Sharing Neural Networks in Cross Technology SRAM Analysis
2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME), IEEE, Taormina, Italy 2025, 2,025
URL, RIS, BibTex
E. Rama,
M. Ayache,
R. Buchty,
B. Bauer,
M. Korb,
M. Berekovic, and
S. Mulhem
Trustworthy Integrated Circuits: From Safety to Security and Beyond
IEEE Access, IEEE, 2024, 2,024
URL, RIS, BibTex
Trustworthy Integrated Circuits: From Safety to Security and Beyond
IEEE Access, IEEE, 2024, 2,024
URL, RIS, BibTex
A. Nechi,
L. Groth,
S. Mulhem,
F. Merchant,
R. Buchty, and
M. Berekovic
FPGA-based Deep Learning Inference Accelerators: Where Are We Standing?
ACM Transactions on Reconfigurable Technology and Systems, 16(4), 1-32, 2,023
RIS, BibTex
FPGA-based Deep Learning Inference Accelerators: Where Are We Standing?
ACM Transactions on Reconfigurable Technology and Systems, 16(4), 1-32, 2,023
RIS, BibTex
H. Lin,
C. Sun,
M. Sheu, and
M. Berekovic
A new low-complexity approximate DCT for image and video compression
Journal of the Chinese Institute of Engineers, 580-591, Chinese Institute of Engineers, Taipei, Taiwan 2020, 2,020
URL, DOI, RIS, BibTex
A new low-complexity approximate DCT for image and video compression
Journal of the Chinese Institute of Engineers, 580-591, Chinese Institute of Engineers, Taipei, Taiwan 2020, 2,020
URL, DOI, RIS, BibTex
R. Meyer,
J. Wagner,
B. Farkas,
S. Horsinka,
P. Siegl,
R. Buchty, and
M. Berekovic
A Scriptable Standard-Compliant Reporting and Logging Framework for SystemC
ACM Trans. Embed. Comput. Syst., 16(1), 2,016
URL, DOI, RIS, BibTex
A Scriptable Standard-Compliant Reporting and Logging Framework for SystemC
ACM Trans. Embed. Comput. Syst., 16(1), 2,016
URL, DOI, RIS, BibTex
P. Bahmanyar,
M. Maymandi-Nejad,
S. Hosseini-Khayat, and
M. Berekovic
Design and Analysis of an Ultra-low-power Double-tail Latched Comparator for Biomedical Applications
Analog Integrated Circuits and Signal Processing, 86(2), 2,016
RIS, BibTex
Design and Analysis of an Ultra-low-power Double-tail Latched Comparator for Biomedical Applications
Analog Integrated Circuits and Signal Processing, 86(2), 2,016
RIS, BibTex
M. Berekovic,
S. Chakraborty,
P. Eles, and
A. D. Pimentel
Introduction to the Special Section on ESTIMedia’08
ACM Transactions in Embedded Computing Systems, 2,012
DOI, RIS, BibTex
Introduction to the Special Section on ESTIMedia’08
ACM Transactions in Embedded Computing Systems, 2,012
DOI, RIS, BibTex
M. Hartmann,
T. V. Aa,
M. Berekovic, and
C. Hochberger
Still Image Processing on Coarse-Grained Reconfigurable Array Architectures
Journal of Signal Processing Systems, 60, 2,010
DOI, RIS, BibTex
Still Image Processing on Coarse-Grained Reconfigurable Array Architectures
Journal of Signal Processing Systems, 60, 2,010
DOI, RIS, BibTex
M. Berekovic,
V. Chaudhary,
A. Dean, and
J. Fritts
Editorial
Microprocess. Microsyst., 33(4), 2,009
DOI, RIS, BibTex
Editorial
Microprocess. Microsyst., 33(4), 2,009
DOI, RIS, BibTex
M. Berekovic,
A. Kanstein,
B. Mei, and
B. D. Sutter
Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor
Microprocessors and Microsystems, 33, 2,009
DOI, RIS, BibTex
Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor
Microprocessors and Microsystems, 33, 2,009
DOI, RIS, BibTex
L. Yseboodt,
M. D. Nil,
J. Huisken,
M. Berekovic,
Q. Zhao,
F. Bouwens,
J. Hulzink, and
J. V. Meerbergen
Design of 100 μW Wireless Sensor Nodes for Biomedical Monitoring
Journal of Signal Processing Systems, 57, 2,009
DOI, RIS, BibTex
Design of 100 μW Wireless Sensor Nodes for Biomedical Monitoring
Journal of Signal Processing Systems, 57, 2,009
DOI, RIS, BibTex
M. Berekovic and
T. Niggemeier
A distributed, simultaneously multi-threaded (SMT) processor with clustered scheduling windows for scalable DSP performance
J. Signal Process. Syst., 50(2), 2,008
DOI, RIS, BibTex
A distributed, simultaneously multi-threaded (SMT) processor with clustered scheduling windows for scalable DSP performance
J. Signal Process. Syst., 50(2), 2,008
DOI, RIS, BibTex
M. Berekovic,
A. D. Pimentel, and
T. D. Hämäläinen
Editorial
J. Syst. Archit., 54(11), 2,008
DOI, RIS, BibTex
Editorial
J. Syst. Archit., 54(11), 2,008
DOI, RIS, BibTex
M. Berekovic,
C. Hochberger, and
A. Koch
Rekonfigurierbare Architekturen
Informatik Spektrum, 31, 2,008
DOI, RIS, BibTex
Rekonfigurierbare Architekturen
Informatik Spektrum, 31, 2,008
DOI, RIS, BibTex
M. Berekovic and
T. Niggemeier
A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance
Journal of Signal Processing Systems, 50, 2,008
DOI, RIS, BibTex
A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance
Journal of Signal Processing Systems, 50, 2,008
DOI, RIS, BibTex
K. Wu,
A. Kanstein,
J. Madsen, and
M. Berekovic
MT-ADRES: multi-threading on coarse-grained reconfigurable architecture
International Journal of Electronics, 95, 2,008
DOI, RIS, BibTex
MT-ADRES: multi-threading on coarse-grained reconfigurable architecture
International Journal of Electronics, 95, 2,008
DOI, RIS, BibTex
S. López,
A. Kanstein,
J. F. López,
M. Berekovic,
R. Sarmiento, and
J.-Y. Mignolet
Toward the implementation of a baseline H.264/AVC decoder onto a reconfigurable architecture
2,007
DOI, RIS, BibTex
Toward the implementation of a baseline H.264/AVC decoder onto a reconfigurable architecture
2,007
DOI, RIS, BibTex
M. D. Nil,
L. Yseboodt,
F. Bouwens,
J. Hulzink,
M. Berekovic,
J. Huisken, and
J. van Meerbergen
Ultra Low Power ASIP Design for Wireless Sensor Nodes
2,007
DOI, RIS, BibTex
Ultra Low Power ASIP Design for Wireless Sensor Nodes
2,007
DOI, RIS, BibTex
M. Berekovic,
A. Kanstein, and
B. Mei
Mapping MPEG Video Decoders on the ADRES Reconfigurable Array Processor for Next Generation MultiMode Mobile Terminals
2,006
RIS, BibTex
Mapping MPEG Video Decoders on the ADRES Reconfigurable Array Processor for Next Generation MultiMode Mobile Terminals
2,006
RIS, BibTex
H.-J. Stolberg,
M. Berekovic, and
P. Pirsch
A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 41, 2,005
DOI, RIS, BibTex
A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 41, 2,005
DOI, RIS, BibTex
H.-J. Stolberg,
M. Berekovic,
S. Moch,
L. Friebe,
M. B. Kulaczewski,
S. Flügel,
H. Klußmann,
A. Dehnhardt,
et al.
HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 41, 2,005
DOI, RIS, BibTex
HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 41, 2,005
DOI, RIS, BibTex
M. Berekovic,
S. Moch, and
P. Pirsch
A scalable, clustered SMT processor for digital signal processing
ACM Sigarch Computer Architecture News, 32, 2,004
DOI, RIS, BibTex
A scalable, clustered SMT processor for digital signal processing
ACM Sigarch Computer Architecture News, 32, 2,004
DOI, RIS, BibTex
S. Moch,
M. Bereković,
H.-J. Stolberg,
L. Friebe,
M. B. Kulaczewski,
A. Dehnhardt, and
P. Pirsch
HIBRID-SOC: a multi-core architecture for image and video applications
ACM Sigarch Computer Architecture News, 32, 2,004
DOI, RIS, BibTex
HIBRID-SOC: a multi-core architecture for image and video applications
ACM Sigarch Computer Architecture News, 32, 2,004
DOI, RIS, BibTex
M. Berekovic,
P. Pirsch,
T. Selinger,
K.-i. Wels,
C. Miro,
A. Lafage,
C. Heer, and
G. Ghigo
Architecture of an Image Rendering CoProcessor for MPEG4 Visual Compositing
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 31, 2,002
DOI, RIS, BibTex
Architecture of an Image Rendering CoProcessor for MPEG4 Visual Compositing
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 31, 2,002
DOI, RIS, BibTex
M. Berekovic,
H.-J. Stolberg, and
P. Pirsch
Multicore system-on-chip architecture for MPEG4 streaming video
IEEE Transactions on Circuits and Systems for Video Technology, 12, 2,002
DOI, RIS, BibTex
Multicore system-on-chip architecture for MPEG4 streaming video
IEEE Transactions on Circuits and Systems for Video Technology, 12, 2,002
DOI, RIS, BibTex
H. J. Stolberg,
M. Berekovic,
P. Pirsch, and
H. Runge
The MPEG4 ad-vanced simple profile-a complexity study
2,001
RIS, BibTex
The MPEG4 ad-vanced simple profile-a complexity study
2,001
RIS, BibTex
M. Berekovic,
H. Kloos, and
P. Pirsch
Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 22, 1,999
DOI, RIS, BibTex
Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 22, 1,999
DOI, RIS, BibTex
C. Heer,
C. Miro,
A. Lafage,
M. Berekovic,
G. Ghigo,
T. Selinger, and
K. I. Wels
Design and architecture of the MPEG4 video rendering co-processor `TANGRAM'
Sealing Technology, 1,999
DOI, RIS, BibTex
Design and architecture of the MPEG4 video rendering co-processor `TANGRAM'
Sealing Technology, 1,999
DOI, RIS, BibTex
S. Bauer,
J. Kneip,
T. Mlasko,
B. Schmale,
J. Vollmer,
A. Hutter, and
M. Berekovic
The MPEG4 Multimedia Coding Standard: Algorithms, Architectures and Applications
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 23, 1,999
DOI, RIS, BibTex
The MPEG4 Multimedia Coding Standard: Algorithms, Architectures and Applications
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 23, 1,999
DOI, RIS, BibTex
M. Berekovic,
H.-j. Stolberg,
M. B. Kulaczewski,
P. Pirsch,
H. Möller,
H. Runge,
J. Kneip, and
B. Stabernack
Instruction Set Extensions for MPEG4 Video
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 23, 1,999
DOI, RIS, BibTex
Instruction Set Extensions for MPEG4 Video
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 23, 1,999
DOI, RIS, BibTex
M. Berekovic,
G. Meyer,
Y. Guo, and
P. Pirsch
Multimedia RISC core for efficient bitstream parsing and VLD
1,998
RIS, BibTex
Multimedia RISC core for efficient bitstream parsing and VLD
1,998
RIS, BibTex
M. Berekovic and
P. Pirsch
Architecture of a coprocessor module for image compositing
Physica Medica, 1,998
DOI, RIS, BibTex
Architecture of a coprocessor module for image compositing
Physica Medica, 1,998
DOI, RIS, BibTex
M. Berekovic,
P. Pirsch, and
J. Kneip
An Algorithm-Hardware-System Approach to VLIW Multimedia Processors
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 20, 1,998
DOI, RIS, BibTex
An Algorithm-Hardware-System Approach to VLIW Multimedia Processors
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 20, 1,998
DOI, RIS, BibTex
P. Pirsch,
A. Freimann, and
M. Berekovic
Architectural approaches for multimedia processors
1,997
RIS, BibTex
Architectural approaches for multimedia processors
1,997
RIS, BibTex
J. Kneip,
M. Berekovic,
J. P. Wittenburg,
W. Hinrichs, and
P. Pirsch
An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 16, 1,997
DOI, RIS, BibTex
An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 16, 1,997
DOI, RIS, BibTex
Conference Papers
H. K. Lin,
W. Foudhaili,
R. Buchty,
M. Berekovic, and
S. Mulhem
Characterising Physical Memory Access Pattern Impact on RISC-V Softcore Performance: A Microbenchmark Study
International Symposium on Applied Reconfigurable Computing, 82-99, Springer Nature Switzerland, Cham, Switzerland 2026, 2,026
URL, DOI, RIS, BibTex
Characterising Physical Memory Access Pattern Impact on RISC-V Softcore Performance: A Microbenchmark Study
International Symposium on Applied Reconfigurable Computing, 82-99, Springer Nature Switzerland, Cham, Switzerland 2026, 2,026
URL, DOI, RIS, BibTex
A. Gutermann,
L. Groth,
A. Neskovic,
S. Mulhem, and
M. Berekovic
Multi-Partner Project: CeCaS Accelerator Design for Efficient Supercomputing in Automotive Systems
2026 Design, Automation & Test in Europe Conference (DATE), IEEE, Verona, Italy 2026, 2,026
URL, RIS, BibTex
Multi-Partner Project: CeCaS Accelerator Design for Efficient Supercomputing in Automotive Systems
2026 Design, Automation & Test in Europe Conference (DATE), IEEE, Verona, Italy 2026, 2,026
URL, RIS, BibTex
J. Bouhlila and
M. Berekovic
In Simplicity There Is Strength: The Unreasonable Effectiveness of XGBoost for Generalizable SRAM Stability Prediction
2026 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, Shanghai, China 2026, 2,026
URL, RIS, BibTex
In Simplicity There Is Strength: The Unreasonable Effectiveness of XGBoost for Generalizable SRAM Stability Prediction
2026 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, Shanghai, China 2026, 2,026
URL, RIS, BibTex
A. Nechi,
Y. Ghafourian,
B. A. Naim,
T. Gutt,
G. Dimitrakopoulos,
A. Moualhi,
M. Berekovic,
P. Varga,
et al.
Multi-Partner Project: Artificial Intelligence in Manufacturing Leading to Sustainability and the Consideration of Human Aspects (AIMS5.0)
2025 Design, Automation & Test in Europe Conference (DATE), IEEE, 2,025
technological innovation cyber-physical systems hardware manufacturing sustainable development artificial intelligence optimization co-pilot
URL, DOI, RIS, BibTex
Multi-Partner Project: Artificial Intelligence in Manufacturing Leading to Sustainability and the Consideration of Human Aspects (AIMS5.0)
2025 Design, Automation & Test in Europe Conference (DATE), IEEE, 2,025
technological innovation cyber-physical systems hardware manufacturing sustainable development artificial intelligence optimization co-pilot
URL, DOI, RIS, BibTex
A. Mahmoudi,
C. Horn,
S. Mulhem,
R. Buchty,
M. Berekovic, and
R. Meyer
TinyML Unleashed: Accelerating TensorFlow Lite Micro Kernels with RISC-V Vector Extension
33rd Telecommunications Forum (TELFOR), IEEE, 2025, 2,025
URL, RIS, BibTex
TinyML Unleashed: Accelerating TensorFlow Lite Micro Kernels with RISC-V Vector Extension
33rd Telecommunications Forum (TELFOR), IEEE, 2025, 2,025
URL, RIS, BibTex
I. Cejic,
A. Neskovic,
M. Berekovic,
S. Mulhem, and
V. Vranjkovic
Area-Optimized RISC-V Matrix Extension Implementation for Edge Devices
33rd Telecommunications Forum (TELFOR), IEEE, 2025, 2,025
URL, RIS, BibTex
Area-Optimized RISC-V Matrix Extension Implementation for Edge Devices
33rd Telecommunications Forum (TELFOR), IEEE, 2025, 2,025
URL, RIS, BibTex
J. Bouhlila,
R. Buchty, and
M. Berekovic
Cross Technology Prediction for SRAM Stability Analysis
2025 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, London, United Kingdom 2025, 2,025
URL, RIS, BibTex
Cross Technology Prediction for SRAM Stability Analysis
2025 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, London, United Kingdom 2025, 2,025
URL, RIS, BibTex
W. Foudhaili,
A. Nechi,
C. Thermann,
M. A. Johmani,
R. uchty,
M. Berekovic, and
S. Mulhem
Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach
Applied Reconfigurable Computing. Architectures, Tools, and Applications, Springer, 2,024
RIS, BibTex
Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach
Applied Reconfigurable Computing. Architectures, Tools, and Applications, Springer, 2,024
RIS, BibTex
D. Hirsch,
F. Hoffmann,
A. Neskovic,
C. Thermann,
R. Buchty,
M. Berekovic, and
S. Mulhem
Efficient AI-based Attack Detection Methods for Sensitive Edge Devices and Systems
Advancing Edge Artificial Intelligence, River Publishers, 2,024
RIS, BibTex
Efficient AI-based Attack Detection Methods for Sensitive Edge Devices and Systems
Advancing Edge Artificial Intelligence, River Publishers, 2,024
RIS, BibTex
M. Roshdi,
J. Petzold,
M. Wahby,
H. Ebrahim,
M. Berekovic, and
H. Hamann
On the Road to Clarity: Exploring Explainable AI for World Models in a Driver Assistance System
2024 1st Conference on Artificial Intelligence, 2,024
RIS, BibTex
On the Road to Clarity: Exploring Explainable AI for World Models in a Driver Assistance System
2024 1st Conference on Artificial Intelligence, 2,024
RIS, BibTex
S. Mulhem,
C. Ewert,
A. Neskovic,
A. Poudel,
C. Hübner,
M. Berekovic, and
R. Buchty
Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip
2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC), IEEE, Tanger, Morocco 2024, 2,024
URL, RIS, BibTex
Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip
2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC), IEEE, Tanger, Morocco 2024, 2,024
URL, RIS, BibTex
J. Bouhlila,
F. Last,
R. Buchty,
M. Berekovic, and
S. Mulhem
Machine Learning for SRAM Stability Analysis
2024 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, IEEE, Singapore 2024, 2,024
URL, RIS, BibTex
Machine Learning for SRAM Stability Analysis
2024 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, IEEE, Singapore 2024, 2,024
URL, RIS, BibTex
M. Ayache,
E. Rama,
S. Mulhem,
M. Berekovic, and
M. Korb
Holistic Framework for Evaluating the Trustworthiness of Integrated Circuits
2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC), IEEE, Tanger, Morocco 2024, 2,024
URL, RIS, BibTex
Holistic Framework for Evaluating the Trustworthiness of Integrated Circuits
2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC), IEEE, Tanger, Morocco 2024, 2,024
URL, RIS, BibTex
A. Nechi,
A. Mahmoudi,
C. Herold,
D. Widmer,
T. Kürner,
M. Berekovic, and
S. Mulhem
Practical Trustworthiness Model for DNN in Dedicated 6G Application
2023 19th International Conference on Wireless and Mobile Computing, Networking and Communications (WiMob), 312-317, 2,023
wireless communication sensitivity 6g communication terahertz band modulation recognition trustworthiness
URL, DOI, RIS, BibTex
Practical Trustworthiness Model for DNN in Dedicated 6G Application
2023 19th International Conference on Wireless and Mobile Computing, Networking and Communications (WiMob), 312-317, 2,023
wireless communication sensitivity 6g communication terahertz band modulation recognition trustworthiness
URL, DOI, RIS, BibTex
J. Petzold,
M. Wahby,
Y. Ziad,
M. ElSheikh,
A. Dawood,
M. Berekovic, and
H. Hamann
Protecting Vulnerable Road Users: Semantic Video Analysis for Accident Prediction
2023 IEEE Symposium Series on Computational Intelligence (SSCI), 2,023
RIS, BibTex
Protecting Vulnerable Road Users: Semantic Video Analysis for Accident Prediction
2023 IEEE Symposium Series on Computational Intelligence (SSCI), 2,023
RIS, BibTex
A. Neskovic,
S. Mulhem,
A. Treff,
R. Buchty,
T. Eisenbarth, and
M. Berekovic
SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not?
in ICCAD '23: Proceedings of the 42nd IEEE/ACM International Conference on Computer-Aided Design, IEEE/ACM, 2023, 2,023
URL, RIS, BibTex
SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not?
in ICCAD '23: Proceedings of the 42nd IEEE/ACM International Conference on Computer-Aided Design, IEEE/ACM, 2023, 2,023
URL, RIS, BibTex
P. Grothe,
S. Mulhem, and
M. Berekovic
An Almost Fully RRAM-Based LUT Design for Reconfigurable Circuits
In: Palumbo, F., Keramidas, G., Voros, N., Diniz, P.C. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2023. Lecture Notes in Computer Science, vol 14251, Springer, Cham 2023, 2,023
URL, DOI, RIS, BibTex
An Almost Fully RRAM-Based LUT Design for Reconfigurable Circuits
In: Palumbo, F., Keramidas, G., Voros, N., Diniz, P.C. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2023. Lecture Notes in Computer Science, vol 14251, Springer, Cham 2023, 2,023
URL, DOI, RIS, BibTex
C. Blochwitz,
P. Grothe,
S. Dreier,
W. Aljnabi,
R. Buchty, and
M. Berekovic
RemEduLa - Remote Education Laboratory for FPGA Design Technology
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 1773-1777, IEEE, 2022, 2,022
URL, RIS, BibTex
RemEduLa - Remote Education Laboratory for FPGA Design Technology
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 1773-1777, IEEE, 2022, 2,022
URL, RIS, BibTex
B. Bauer,
M. Ayache,
S. Mulhem,
M. Nitzan,
J. Athavale,
R. Buchty, and
M. Berekovic
On the Dependability Lifecycle of Electrical/Electronic Product Development: The Dual-Cone V-Model
in Computer, vol. 55, no. 9, 99-106, 2022, 2,022
URL, DOI, RIS, BibTex
On the Dependability Lifecycle of Electrical/Electronic Product Development: The Dual-Cone V-Model
in Computer, vol. 55, no. 9, 99-106, 2022, 2,022
URL, DOI, RIS, BibTex
R. Zarrouk,
S. Mulhem,
W. Adi, and
M. Berekovic
Clone-Resistant Secured Booting Based on Unknown Hashing Created in Self-Reconfigurable Platform
In: Derrien S., Hannig F., Diniz P.C., Chillet D. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2021. Lecture Notes in Computer Science, vol 12700, Springer, Cham 2021, 2,021
URL, DOI, RIS, BibTex
Clone-Resistant Secured Booting Based on Unknown Hashing Created in Self-Reconfigurable Platform
In: Derrien S., Hannig F., Diniz P.C., Chillet D. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2021. Lecture Notes in Computer Science, vol 12700, Springer, Cham 2021, 2,021
URL, DOI, RIS, BibTex
E. Hamadaqa,
S. Mulhem,
W. Adi, and
M. Berekovic
Contemporary Physical Clone-Resistant Identity for IoTs and Emerging Technologies
Cryptography 2021, 2021, 2,021
URL, DOI, RIS, BibTex
Contemporary Physical Clone-Resistant Identity for IoTs and Emerging Technologies
Cryptography 2021, 2021, 2,021
URL, DOI, RIS, BibTex
A. Dörflinger,
M. Albers,
B. Kleinbeck,
Y. Guan,
H. Michalik,
R. Klink,
C. Blochwitz,
A. Nechi,
et al.
A comparative survey of open-source application-class RISC-V processor implementations
CF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers, ACM, 2021, 2,021
URL, DOI, RIS, BibTex
A comparative survey of open-source application-class RISC-V processor implementations
CF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers, ACM, 2021, 2,021
URL, DOI, RIS, BibTex
C. Blochwitz,
L. Philipp,
M. Berekovic, and
P. T.
StreamGrid - An AXI-Stream-Compliant Overlay Architecture
International Symposium on Applied Reconfigurable Computing, ARC 2021, 156-170, Springer, Cham, 2021, 2,021
URL, RIS, BibTex
StreamGrid - An AXI-Stream-Compliant Overlay Architecture
International Symposium on Applied Reconfigurable Computing, ARC 2021, 156-170, Springer, Cham, 2021, 2,021
URL, RIS, BibTex
H. Hamann,
M. Berekovic,
N. Stoll,
M. I. Ali, and
H. F. M. El-sayed
Guest Editorial: Evolutionary Computation for Image Processing (Retracted article. See vol. 17, pg. 301, 2023)
Evolutionary Computation for Image Processing, WILEY, 2020, 2,020
URL, RIS, BibTex
Guest Editorial: Evolutionary Computation for Image Processing (Retracted article. See vol. 17, pg. 301, 2023)
Evolutionary Computation for Image Processing, WILEY, 2020, 2,020
URL, RIS, BibTex
P. Jungklass and
M. Berekovic
Cache-Kohärenz für embedded Multicore-Mikrocontroller mit harter Echtzeitanforderung
Echtzeit 2019, 129-138, Springer Vieweg, Wiesbaden 2019, 2,019
URL, DOI, RIS, BibTex
Cache-Kohärenz für embedded Multicore-Mikrocontroller mit harter Echtzeitanforderung
Echtzeit 2019, 129-138, Springer Vieweg, Wiesbaden 2019, 2,019
URL, DOI, RIS, BibTex
P. Jungklass and
M. Berekovic
MemOpt: Automated Memory Distribution for Multicore Microcontrollers with Hard Real-Time Requirements
2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), IEEE, Helsinki, Finland 2019, 2,019
URL, RIS, BibTex
MemOpt: Automated Memory Distribution for Multicore Microcontrollers with Hard Real-Time Requirements
2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), IEEE, Helsinki, Finland 2019, 2,019
URL, RIS, BibTex
C. Blochwitz,
J. Wolff,
M. Berekovic,
D. Heinrich,
S. Groppe,
J. Joseph, and
P. T.
Hardware-Triplestore – a Hardware-centric Database for Semantic Web
International Conference on Field-Programmable Technology, 2018, 2,018
RIS, BibTex
Hardware-Triplestore – a Hardware-centric Database for Semantic Web
International Conference on Field-Programmable Technology, 2018, 2,018
RIS, BibTex
M. Berekovic,
R. Buchty,
H. Hamann,
D. Koch, and
P. T.
Architecture of Computing Systems-ARCS 2018
Architecture of Computing Systems-ARCS 2018, Springer International Publishing, 2018, 2,018
URL, DOI, RIS, BibTex
Architecture of Computing Systems-ARCS 2018
Architecture of Computing Systems-ARCS 2018, Springer International Publishing, 2018, 2,018
URL, DOI, RIS, BibTex
L. Mattii,
D. M. Milojevic,
P. Debacker,
Y. Sherazi,
M. Berekovic, and
P. Raghavan
IR-drop aware Design technology co-optimization for N5 node with different device and cell height options
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2,017
DOI, RIS, BibTex
IR-drop aware Design technology co-optimization for N5 node with different device and cell height options
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2,017
DOI, RIS, BibTex
P. Siegl,
R. Buchty, and
M. Berekovic
A Bandwidth Accurate, Flexible and Rapid Simulating Multi-HMC Modelling Tool
Proceedings of the Third International Symposium on Memory Systems, MEMSYS 2017, Washington, DC, USA, October 2-5, 2017, ACM, 2,017, ISBN 978-1-4503-5335-9/17/10
DOI, ISBN, RIS, BibTex
A Bandwidth Accurate, Flexible and Rapid Simulating Multi-HMC Modelling Tool
Proceedings of the Third International Symposium on Memory Systems, MEMSYS 2017, Washington, DC, USA, October 2-5, 2017, ACM, 2,017, ISBN 978-1-4503-5335-9/17/10
DOI, ISBN, RIS, BibTex
R. Meyer,
B. Farkas,
S. A. A. Shah, and
M. Berekovic
Transparent SystemC Model Factory for Scripting Languages
Design and Verification Conference (DVCon) United States 2017, February 27 - March 2, 2017 , San Jose, CA USA, 2,017
RIS, BibTex
Transparent SystemC Model Factory for Scripting Languages
Design and Verification Conference (DVCon) United States 2017, February 27 - March 2, 2017 , San Jose, CA USA, 2,017
RIS, BibTex
H. Isakovic,
R. Grosu,
D. Ratasich,
J. Kadlec,
Z. Pohl,
S. Kerrison,
K. Georgiou,
K. Eder,
et al.
A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC^2
Computer Safety, Reliability, and Security - SAFECOMP 2017 Workshops, ASSURE, DECSoS, SASSUR, TELERISE, and TIPS, Trento, Italy, September 12, 2017, Proceedings, 2,017
URL, DOI, RIS, BibTex
A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC^2
Computer Safety, Reliability, and Security - SAFECOMP 2017 Workshops, ASSURE, DECSoS, SASSUR, TELERISE, and TIPS, Trento, Italy, September 12, 2017, Proceedings, 2,017
URL, DOI, RIS, BibTex
S. A. A. Shah,
S. Horsinka,
B. Farkas,
R. Meyer, and
M. Berekovic
Automatic Exploration of Hardware/Software Partitioning
Design and Verification Conference (DVCon) United States 2017, February 27 - March 2, 2017 , San Jose, CA USA, 2,017
RIS, BibTex
Automatic Exploration of Hardware/Software Partitioning
Design and Verification Conference (DVCon) United States 2017, February 27 - March 2, 2017 , San Jose, CA USA, 2,017
RIS, BibTex
S. A. A. Shah,
B. Farkas,
R. Meyer, and
M. Berekovic
Accelerating MPSoC Design Space Exploration Within System-Level Frameworks
The IEEE Nordic Circuits and Systems Conference (NORCAS), 1-2 November 2016 Copenhagen, Denmark, 2,016
RIS, BibTex
Accelerating MPSoC Design Space Exploration Within System-Level Frameworks
The IEEE Nordic Circuits and Systems Conference (NORCAS), 1-2 November 2016 Copenhagen, Denmark, 2,016
RIS, BibTex
B. Farkas,
S. A. A. Shah,
J. Wagner,
R. Meyer,
R. Buchty, and
M. Berekovic
An Open and Flexible SystemC to VHDL Workflow for Rapid Prototyping
Design and Verification Conference (DVCon) Europe 2016, October 19 - 20, 2016 Munich, Germany, 2,016
RIS, BibTex
An Open and Flexible SystemC to VHDL Workflow for Rapid Prototyping
Design and Verification Conference (DVCon) Europe 2016, October 19 - 20, 2016 Munich, Germany, 2,016
RIS, BibTex
P. Siegl,
R. Buchty, and
M. Berekovic
Data-Centric Computing Frontiers: A Survey On Processing-In-Memory
Proceedings of the Second International Symposium on Memory Systems, MEMSYS 2016, Washington, DC, USA, October 3-6, 2016, ACM, 2,016, ISBN 978-1-4503-4305-3
DOI, ISBN, RIS, BibTex
Data-Centric Computing Frontiers: A Survey On Processing-In-Memory
Proceedings of the Second International Symposium on Memory Systems, MEMSYS 2016, Washington, DC, USA, October 3-6, 2016, ACM, 2,016, ISBN 978-1-4503-4305-3
DOI, ISBN, RIS, BibTex
J. Naghmouchi,
S. Michalik,
R. Scheiber,
A. Reigber,
P. Aviely,
R. Ginosar,
O. Bischoff,
H. Gellis,
et al.
MacSpace - High-performance DSP for onboard image processing
DSP Day: COTS DSP chips and boards, 2,016
URL, RIS, BibTex
MacSpace - High-performance DSP for onboard image processing
DSP Day: COTS DSP chips and boards, 2,016
URL, RIS, BibTex
P. Siegl,
R. Buchty, and
M. Berekovic
Towards Bridging the Gap Between Academic and Industrial Heterogeneous System Architecture Design Space Exploration
Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation - Methods and Tools, RAPIDO@HiPEAC 2016, Prague, Czech Republic, January 18, 2016, ACM, 2,016, ISBN 978-1-4503-4072-4
URL, DOI, ISBN, RIS, BibTex
Towards Bridging the Gap Between Academic and Industrial Heterogeneous System Architecture Design Space Exploration
Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation - Methods and Tools, RAPIDO@HiPEAC 2016, Prague, Czech Republic, January 18, 2016, ACM, 2,016, ISBN 978-1-4503-4072-4
URL, DOI, ISBN, RIS, BibTex
P. Siegl,
R. Buchty,
B. Farkas,
S. A. Horsinka,
R. Meyer,
J. Wagner, and
M. Berekovic
The Past, Present and Future of the Open-Source Virtual Platform SoCRocket
Proceedings of the 2016 Workshop on Mixed Criticality Applications and Implementation Approaches, EMC^2@HiPEAC 2016, Prague, Czech Republic, January 20, 2016, 2,016
RIS, BibTex
The Past, Present and Future of the Open-Source Virtual Platform SoCRocket
Proceedings of the 2016 Workshop on Mixed Criticality Applications and Implementation Approaches, EMC^2@HiPEAC 2016, Prague, Czech Republic, January 20, 2016, 2,016
RIS, BibTex
R. Meyer,
J. Wagner,
R. Buchty, and
M. Berekovic
Universal Scripting Interface for SystemC
DVCon Europe Conference Proceedings 2015, 2,015
URL, RIS, BibTex
Universal Scripting Interface for SystemC
DVCon Europe Conference Proceedings 2015, 2,015
URL, RIS, BibTex
J. Wagner,
R. Meyer,
R. Buchty, and
M. Berekovic
A scriptable, standards-compliant reporting and logging extension for SystemC
Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on, 2,015
URL, DOI, RIS, BibTex
A scriptable, standards-compliant reporting and logging extension for SystemC
Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on, 2,015
URL, DOI, RIS, BibTex
J. Naghmouchi,
P. Aviely,
R. Ginosar,
G. Over,
O. Bischoff,
R. Nadler,
D. Guiser,
M. Citroen,
et al.
QI2S - Quick Image Interpretation System
Data Systems in Aerospace, Proceedings of the conference, ESA-SP Vol. 732, 2015, id.51, 2,015
URL, RIS, BibTex
QI2S - Quick Image Interpretation System
Data Systems in Aerospace, Proceedings of the conference, ESA-SP Vol. 732, 2015, id.51, 2,015
URL, RIS, BibTex
S. Michalik,
R. Meyer,
S. Michalik,
P. Siegl,
M. Berekovic, and
L. Fossati
TLM Design Space Exploration for a Hardware CFDP Transmission Accelerator
SEA-Publications, 2,015
RIS, BibTex
TLM Design Space Exploration for a Hardware CFDP Transmission Accelerator
SEA-Publications, 2,015
RIS, BibTex
P. Siegl,
R. Buchty, and
M. Berekovic
Revealing Potential Performance Improvements By Utilizing Hybrid Work-Sharing For Resource-Intensive Seismic Applications
Proceedings of the 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015, Turku, Finland, March 4-6, 2015, IEEE Computer Society, 2,015, ISBN 978-1-4799-8490-9
URL, DOI, ISBN, RIS, BibTex
Revealing Potential Performance Improvements By Utilizing Hybrid Work-Sharing For Resource-Intensive Seismic Applications
Proceedings of the 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015, Turku, Finland, March 4-6, 2015, IEEE Computer Society, 2,015, ISBN 978-1-4799-8490-9
URL, DOI, ISBN, RIS, BibTex
S. Qin and
M. Berekovic
A Comparison of High-Level Design Tools for SoC-FPGA on Disparity Map Calculation Example
CoRR, 150,900,036, 2,015
URL, RIS, BibTex
A Comparison of High-Level Design Tools for SoC-FPGA on Disparity Map Calculation Example
CoRR, 150,900,036, 2,015
URL, RIS, BibTex
T. Schuster,
R. Meyer,
R. Buchty,
L. Fossati, and
M. Berekovic
SoCRocket - A virtual platform for the European Space Agency's SoC development
Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014 9th International Symposium on, 2,014
DOI, RIS, BibTex
SoCRocket - A virtual platform for the European Space Agency's SoC development
Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014 9th International Symposium on, 2,014
DOI, RIS, BibTex
I. Tsekoura,
G. Rebel,
P. Glosekotter, and
M. Berekovic
An evaluation of energy efficient microcontrollers
Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014 9th International Symposium on, 2,014
DOI, RIS, BibTex
An evaluation of energy efficient microcontrollers
Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014 9th International Symposium on, 2,014
DOI, RIS, BibTex
H. Al-Khalissi,
S. A. A. Shah, and
M. Berekovic
An Efficient Barrier Implementation for OpenMP-Like Parallelism on the Intel SCC
PDP '14: Proceedings of the 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, IEEE Computer Society, 2,014, ISBN 978-1-4799-2729-6
DOI, ISBN, RIS, BibTex
An Efficient Barrier Implementation for OpenMP-Like Parallelism on the Intel SCC
PDP '14: Proceedings of the 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, IEEE Computer Society, 2,014, ISBN 978-1-4799-2729-6
DOI, ISBN, RIS, BibTex
H. Al-Khalissi,
M. Berekovic, and
A. Marongiu
On the Relevance of Architectural Awareness for Efficient Fork/Join Support on Cluster-Based Manycores
MES '14: Proceedings of International Workshop on Manycore Embedded Systems, ACM, 2,014, ISBN 978-1-4503-2822-7
DOI, ISBN, RIS, BibTex
On the Relevance of Architectural Awareness for Efficient Fork/Join Support on Cluster-Based Manycores
MES '14: Proceedings of International Workshop on Manycore Embedded Systems, ACM, 2,014, ISBN 978-1-4503-2822-7
DOI, ISBN, RIS, BibTex
S. A. Horsinka,
R. Meyer,
J. Wagner,
R. Buchty, and
M. Berekovic
On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design Exploration
NoCArc '14: Proceedings of the 2014 International Workshop on Network on Chip Architectures, ACM, 2,014, ISBN 978-1-4503-3064-0
DOI, ISBN, RIS, BibTex
On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design Exploration
NoCArc '14: Proceedings of the 2014 International Workshop on Network on Chip Architectures, ACM, 2,014, ISBN 978-1-4503-3064-0
DOI, ISBN, RIS, BibTex
S. A. A. Shah,
J. Wagner,
T. Schuster, and
M. Berekovic
A lightweight-system-level power and area estimation methodology for application specific instruction set processors
Power and Timing Modeling, Optimization and Simulation (PATMOS), 2014 24th International Workshop on, 2,014
DOI, RIS, BibTex
A lightweight-system-level power and area estimation methodology for application specific instruction set processors
Power and Timing Modeling, Optimization and Simulation (PATMOS), 2014 24th International Workshop on, 2,014
DOI, RIS, BibTex
B. Farkas,
H. Schrom, and
M. Berekovic
BEM: Der Building-Energy-Manager fuer das Smart-Home der Zukunft
VDE Kongress 2014, 2,014
RIS, BibTex
BEM: Der Building-Energy-Manager fuer das Smart-Home der Zukunft
VDE Kongress 2014, 2,014
RIS, BibTex
J. Wagner,
R. Buchty,
C. Schubert, and
M. Berekovic
Designing a low-power wireless sensor node rASIP architecture
Signal Processing Systems (SiPS), 2013 IEEE Workshop on, 2,013
DOI, RIS, BibTex
Designing a low-power wireless sensor node rASIP architecture
Signal Processing Systems (SiPS), 2013 IEEE Workshop on, 2,013
DOI, RIS, BibTex
B. Motruk,
J. Diemer,
R. Buchty, and
M. Berekovic
Power monitoring for mixed-criticality on a many-core platform
ARCS'13: Proceedings of the 26th international conference on Architecture of Computing Systems, Springer-Verlag, 2,013, ISBN 978-3-642-36423-5
DOI, ISBN, RIS, BibTex
Power monitoring for mixed-criticality on a many-core platform
ARCS'13: Proceedings of the 26th international conference on Architecture of Computing Systems, Springer-Verlag, 2,013, ISBN 978-3-642-36423-5
DOI, ISBN, RIS, BibTex
B. Motruk,
J. Diemer,
P. Axer,
R. Buchty, and
M. Berekovic
Safe Virtual Interrupts Leveraging Distributed Shared Resources and Core-to-Core Communication on Many-Core Platforms
PRDC '13: Proceedings of the 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing, IEEE Computer Society, 2,013, ISBN 978-0-7695-5130-2
DOI, ISBN, RIS, BibTex
Safe Virtual Interrupts Leveraging Distributed Shared Resources and Core-to-Core Communication on Many-Core Platforms
PRDC '13: Proceedings of the 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing, IEEE Computer Society, 2,013, ISBN 978-0-7695-5130-2
DOI, ISBN, RIS, BibTex
H. Al-Khalissi,
A. Marongiu, and
M. Berekovic
An approach for Supporting OpenMP on the Intel SCC
SPLASH-MARC, 2,013
RIS, BibTex
An approach for Supporting OpenMP on the Intel SCC
SPLASH-MARC, 2,013
RIS, BibTex
H. Al-Khalissi,
R. Buchty, and
M. Berekovic
Efficient Barrier Synchronization for OpenMP-Like Parallelism on the Intel SCC
ICPADS '13: Proceedings of the 2013 International Conference on Parallel and Distributed Systems, IEEE Computer Society, 2,013, ISBN 978-1-4799-2081-5
DOI, ISBN, RIS, BibTex
Efficient Barrier Synchronization for OpenMP-Like Parallelism on the Intel SCC
ICPADS '13: Proceedings of the 2013 International Conference on Parallel and Distributed Systems, IEEE Computer Society, 2,013, ISBN 978-1-4799-2081-5
DOI, ISBN, RIS, BibTex
L. Fossati,
T. Schuster,
R. Meyer, and
M. Berekovic
SoCRocket: A virtual platform for SoC design
Proceedings of DASIA 2013 : DAta Systems In Aerospace : 14-16 May 2013, Porto, Portugal, 2,013
RIS, BibTex
SoCRocket: A virtual platform for SoC design
Proceedings of DASIA 2013 : DAta Systems In Aerospace : 14-16 May 2013, Porto, Portugal, 2,013
RIS, BibTex
B. Motruk,
J. Diemer,
R. Buchty,
R. Ernst, and
M. Berekovic
IDAMC: A Many-Core Platform with Run-Time Monitoring for Mixed-Criticality
HASE '12: Proceedings of the 2012 IEEE 14th International Symposium on High-Assurance Systems Engineering, IEEE Computer Society, 2,012, ISBN 978-0-7695-4912-5
DOI, ISBN, RIS, BibTex
IDAMC: A Many-Core Platform with Run-Time Monitoring for Mixed-Criticality
HASE '12: Proceedings of the 2012 IEEE 14th International Symposium on High-Assurance Systems Engineering, IEEE Computer Society, 2,012, ISBN 978-0-7695-4912-5
DOI, ISBN, RIS, BibTex
H. Al-Khalissi,
A. Marongiu, and
M. Berekovic
Low-Overhead Barrier Synchronization for OpenMP-like Parallelism on the Single-Chip Cloud Computer
Many-core Applications Research Community (MARC) Symposium at RWTH Aachen University, 2,012
RIS, BibTex
Low-Overhead Barrier Synchronization for OpenMP-like Parallelism on the Single-Chip Cloud Computer
Many-core Applications Research Community (MARC) Symposium at RWTH Aachen University, 2,012
RIS, BibTex
H. Al-Khalissi and
M. Berekovic
Performance of RCCE Broadcast Algorithm in SCC
MARC Symposium, 2,011
RIS, BibTex
Performance of RCCE Broadcast Algorithm in SCC
MARC Symposium, 2,011
RIS, BibTex
J. Naghmouchi,
D. P. Scarpazza, and
M. Berekovic
Small-ruleset regular expression matching on GPGPUs: quantitative performance analysis and optimization
ICS '10: Proceedings of the 24th ACM International Conference on Supercomputing, ACM, 2,010, ISBN 978-1-4503-0018-6
DOI, ISBN, RIS, BibTex
Small-ruleset regular expression matching on GPGPUs: quantitative performance analysis and optimization
ICS '10: Proceedings of the 24th ACM International Conference on Supercomputing, ACM, 2,010, ISBN 978-1-4503-0018-6
DOI, ISBN, RIS, BibTex
T. Kranich and
M. Berekovic
NoC Switch with Credit Based Guaranteed Service Support Qualified for GALS Systems
DSD '10: Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, IEEE Computer Society, 2,010, ISBN 978-0-7695-4171-6
DOI, ISBN, RIS, BibTex
NoC Switch with Credit Based Guaranteed Service Support Qualified for GALS Systems
DSD '10: Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, IEEE Computer Society, 2,010, ISBN 978-0-7695-4171-6
DOI, ISBN, RIS, BibTex
D. Bode,
M. Berekovic,
A. Borkowski, and
L. Buker
QoR Analysis of Automated Clock-Mesh Implementation under OCV Consideration
Euromicro Symposium on Digital Systems Design, 2,010
DOI, RIS, BibTex
QoR Analysis of Automated Clock-Mesh Implementation under OCV Consideration
Euromicro Symposium on Digital Systems Design, 2,010
DOI, RIS, BibTex
C. Bachmann,
A. Genser,
J. Hulzink,
M. Berekovic, and
C. Steger
A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing
DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe, European Design and Automation Association, 2,009, ISBN 978-3-9810801-5-5
ISBN, RIS, BibTex
A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing
DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe, European Design and Automation Association, 2,009, ISBN 978-3-9810801-5-5
ISBN, RIS, BibTex
A. Genser,
C. Bachmann,
C. Steger,
J. Hulzink, and
M. Berekovic
Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing
ASAP '09: Proceedings of the 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, IEEE Computer Society, 2,009, ISBN 978-0-7695-3732-0
DOI, ISBN, RIS, BibTex
Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing
ASAP '09: Proceedings of the 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, IEEE Computer Society, 2,009, ISBN 978-0-7695-3732-0
DOI, ISBN, RIS, BibTex
M. Berekovic,
M. Hanke,
T. Schuster,
T. Kranich, and
R. Ernst
ESL design in the context of embedded systems education
WESE '09: Proceedings of the 2009 Workshop on Embedded Systems Education, ACM, 2,009, ISBN 978-1-4503-0021-6
DOI, ISBN, RIS, BibTex
ESL design in the context of embedded systems education
WESE '09: Proceedings of the 2009 Workshop on Embedded Systems Education, ACM, 2,009, ISBN 978-1-4503-0021-6
DOI, ISBN, RIS, BibTex
E. Ladis,
I. Papaefstathiou,
R. Marchesani,
K. Tuinenbreijer,
P. Langendorfer,
T. Zahariadis,
H. C. Leligou,
L. Redondo,
et al.
Secure, Mobile Visual Sensor Networks Architecture
SECON Workshops IEEE Annual Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks Workshops, 2,009
DOI, RIS, BibTex
Secure, Mobile Visual Sensor Networks Architecture
SECON Workshops IEEE Annual Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks Workshops, 2,009
DOI, RIS, BibTex
J. Govers,
J. Huisken,
M. Berekovic,
O. Rousseaux,
F. Bouwens,
M. de Nil, and
J. V. Meerbergen
Implementation of an UWB impulse-radio acquisition and despreading algorithm on a low power ASIP
HiPEAC'08: Proceedings of the 3rd international conference on High performance embedded architectures and compilers, Springer-Verlag, 2,008, ISBN 3-540-77559-5, 978-3-540-77559-1
ISBN, RIS, BibTex
Implementation of an UWB impulse-radio acquisition and despreading algorithm on a low power ASIP
HiPEAC'08: Proceedings of the 3rd international conference on High performance embedded architectures and compilers, Springer-Verlag, 2,008, ISBN 3-540-77559-5, 978-3-540-77559-1
ISBN, RIS, BibTex
F. Bouwens,
M. Berekovic,
B. D. Sutter, and
G. Gaydadjiev
Architecture enhancements for the ADRES coarse-grained reconfigurable array
HiPEAC'08: Proceedings of the 3rd international conference on High performance embedded architectures and compilers, Springer-Verlag, 2,008, ISBN 3-540-77559-5, 978-3-540-77559-1
ISBN, RIS, BibTex
Architecture enhancements for the ADRES coarse-grained reconfigurable array
HiPEAC'08: Proceedings of the 3rd international conference on High performance embedded architectures and compilers, Springer-Verlag, 2,008, ISBN 3-540-77559-5, 978-3-540-77559-1
ISBN, RIS, BibTex
F. Pratas,
G. Gaydadjiev,
M. Berekovic,
L. Sousa, and
S. Kaxiras
Low power microarchitecture with instruction reuse
CF '08: Proceedings of the 5th conference on Computing frontiers, ACM, 2,008, ISBN 978-1-60558-077-7
DOI, ISBN, RIS, BibTex
Low power microarchitecture with instruction reuse
CF '08: Proceedings of the 5th conference on Computing frontiers, ACM, 2,008, ISBN 978-1-60558-077-7
DOI, ISBN, RIS, BibTex
A. Garcia,
M. Berekovic, and
T. V. Aa
Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor
ASAP '08: Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors, IEEE Computer Society, 2,008, ISBN 978-1-4244-1897-8
DOI, ISBN, RIS, BibTex
Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor
ASAP '08: Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors, IEEE Computer Society, 2,008, ISBN 978-1-4244-1897-8
DOI, ISBN, RIS, BibTex
M. Berekovic,
N. J. Dimopoulos, and
S. Wong
Embedded Computer Systems: Architectures, Modeling, and Simulation, 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008. Proceedings
Systems, Architectures, Modeling, and Simulation, 2,008
RIS, BibTex
Embedded Computer Systems: Architectures, Modeling, and Simulation, 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008. Proceedings
Systems, Architectures, Modeling, and Simulation, 2,008
RIS, BibTex
C. Arbelo,
A. Kanstein,
S. Lopez,
J. Lopez,
M. Berekovic,
R. Sarmiento, and
J.-Y. Mignolet
Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: the H.264/AVC Deblocking Filter
Design, Automation Test in Europe Conference Exhibition, 2007. DATE '07, 2,007
DOI, RIS, BibTex
Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: the H.264/AVC Deblocking Filter
Design, Automation Test in Europe Conference Exhibition, 2007. DATE '07, 2,007
DOI, RIS, BibTex
F. Bouwens,
M. Berekovic,
A. Kanstein, and
G. Gaydadjiev
Architectural exploration of the ADRES coarse-grained reconfigurable array
ARC'07: Proceedings of the 3rd international conference on Reconfigurable computing, Springer-Verlag, 2,007, ISBN 978-3-540-71430-9
ISBN, RIS, BibTex
Architectural exploration of the ADRES coarse-grained reconfigurable array
ARC'07: Proceedings of the 3rd international conference on Reconfigurable computing, Springer-Verlag, 2,007, ISBN 978-3-540-71430-9
ISBN, RIS, BibTex
L. Yseboodt,
M. D. Nil,
J. Huisken,
M. Berekovic,
Q. Zhao,
F. Bouwens, and
J. V. Meerbergen
Design of 100 \μ\W wireless sensor nodes on energy scavengers for biomedical monitoring
SAMOS'07: Proceedings of the 7th international conference on Embedded computer systems, Springer-Verlag, 2,007, ISBN 3-540-73622-0, 978-3-540-73622-6
ISBN, RIS, BibTex
Design of 100 \μ\W wireless sensor nodes on energy scavengers for biomedical monitoring
SAMOS'07: Proceedings of the 7th international conference on Embedded computer systems, Springer-Verlag, 2,007, ISBN 3-540-73622-0, 978-3-540-73622-6
ISBN, RIS, BibTex
M. Berekovic
Ulta-Low-Power Wireless Sensor Node Design on 100 uW Scavenging Energy for Applications In Biomedical Monitoring
DSD '07: Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, IEEE Computer Society, 2,007, ISBN 0-7695-2978-X
DOI, ISBN, RIS, BibTex
Ulta-Low-Power Wireless Sensor Node Design on 100 uW Scavenging Energy for Applications In Biomedical Monitoring
DSD '07: Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, IEEE Computer Society, 2,007, ISBN 0-7695-2978-X
DOI, ISBN, RIS, BibTex
L. Yseboodt,
M. D. Nil, and
M. Berekovic
Electrocardiogram on Wireless Sensor Nodes
Dagstuhl Seminars, 2,007
RIS, BibTex
Electrocardiogram on Wireless Sensor Nodes
Dagstuhl Seminars, 2,007
RIS, BibTex
S. Vassiliadis,
M. Berekovic, and
T. D. Hämäläinen
Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings
Systems, Architectures, Modeling, and Simulation, 2,007
RIS, BibTex
Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings
Systems, Architectures, Modeling, and Simulation, 2,007
RIS, BibTex
M. Hartmann,
T. V. Aa,
M. Berekovic,
C. Hochberger, and
B. D. Sutter
Still Image Processing on Coarse-Grained Reconfigurable Array Architectures
Embedded Systems for Real-Time Multimedia, 2,007
DOI, RIS, BibTex
Still Image Processing on Coarse-Grained Reconfigurable Array Architectures
Embedded Systems for Real-Time Multimedia, 2,007
DOI, RIS, BibTex
L. Yseboodt,
M. D. Nil,
J. Huisken,
M. Berekovic,
Q. Zhao,
F. Bouwens, and
J. V. Meerbergen
Design of 100 μW wireless sensor nodes on energy scavengers for biomedical monitoring
SAMOS`07: Proceedings of the 7th international conference on Embedded computer systems, Springer-Verlag, 2007, 2,007
RIS, BibTex
Design of 100 μW wireless sensor nodes on energy scavengers for biomedical monitoring
SAMOS`07: Proceedings of the 7th international conference on Embedded computer systems, Springer-Verlag, 2007, 2,007
RIS, BibTex
M. Berekovic and
T. Niggemeier
A scalable, multi-thread, multi-issue array processor architecture for DSP applications based on extended tomasulo scheme
SAMOS'06: Proceedings of the 6th international conference on Embedded Computer Systems, Springer-Verlag, 2,006, ISBN 3-540-36410-2, 978-3-540-36410-8
DOI, ISBN, RIS, BibTex
A scalable, multi-thread, multi-issue array processor architecture for DSP applications based on extended tomasulo scheme
SAMOS'06: Proceedings of the 6th international conference on Embedded Computer Systems, Springer-Verlag, 2,006, ISBN 3-540-36410-2, 978-3-540-36410-8
DOI, ISBN, RIS, BibTex
H.-J. Stolberg,
S. Moch,
L. Friebe,
A. Dehnhardt,
M. B. Kulaczewski,
M. Berekovic, and
P. Pirsch
An SoC with two multimedia DSPs and a RISC core for video compression applications
Solid-State Circuits IEEE International Conference, 2,004
DOI, RIS, BibTex
An SoC with two multimedia DSPs and a RISC core for video compression applications
Solid-State Circuits IEEE International Conference, 2,004
DOI, RIS, BibTex
H.-J. Stolberg,
M. Berekovic,
L. Friebe,
S. Moch,
S. Flugel,
X. Mao,
M. B. Kulaczewski,
H. Klusmann,
et al.
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications
DATE '03: Proceedings of the conference on Design, Automation and Test in Europe, IEEE Computer Society, 2,003, ISBN 0-7695-1870-2
ISBN, RIS, BibTex
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications
DATE '03: Proceedings of the conference on Design, Automation and Test in Europe, IEEE Computer Society, 2,003, ISBN 0-7695-1870-2
ISBN, RIS, BibTex
M. Berekovic,
S. Moch, and
P. Pirsch
A scalable, clustered SMT processor for digital signal processing
MEDEA '03: Proceedings of the 2003 workshop on MEmory performance, ACM, 2,003
DOI, RIS, BibTex
A scalable, clustered SMT processor for digital signal processing
MEDEA '03: Proceedings of the 2003 workshop on MEmory performance, ACM, 2,003
DOI, RIS, BibTex
S. Moch,
M. Bereković,
H. J. Stolberg,
L. Friebe,
M. B. Kulaczewski,
A. Dehnhardt, and
P. Pirsch
HIBRID-SOC: a multi-core architecture for image and video applications
MEDEA '03: Proceedings of the 2003 workshop on MEmory performance, ACM, 2,003
DOI, RIS, BibTex
HIBRID-SOC: a multi-core architecture for image and video applications
MEDEA '03: Proceedings of the 2003 workshop on MEmory performance, ACM, 2,003
DOI, RIS, BibTex
H.-J. Stolberg,
M. Berekovic,
L. Friebe,
S. Moch,
M. B. Kulaczewski,
A. Dehnhardt, and
P. Pirsch
HiBRID-SoC: a multi-core SoC architecture for multimedia signal processing
IEEE Workshop on Signal Processing Systems, 2,003
DOI, RIS, BibTex
HiBRID-SoC: a multi-core SoC architecture for multimedia signal processing
IEEE Workshop on Signal Processing Systems, 2,003
DOI, RIS, BibTex
L. Friebe,
H.-J. Stolberg,
M. Berekovic,
S. Moch,
M. B. Kulaczewski,
A. Dehnhardt, and
R. Pirsch
HiBRID-SoC: a system-on-chip architecture with two multimedia DSPs and a RISC core
IEEE International System-on-Chip (SoC) Conference, 2,003
DOI, RIS, BibTex
HiBRID-SoC: a system-on-chip architecture with two multimedia DSPs and a RISC core
IEEE International System-on-Chip (SoC) Conference, 2,003
DOI, RIS, BibTex
P. Pirsch,
M. Berekovic,
H.-J. Stolberg, and
J. Jachalsky
VLSI architectures for MPEG
International Symposium on VLSI Technology, Systems and Applications, 2,003
DOI, RIS, BibTex
VLSI architectures for MPEG
International Symposium on VLSI Technology, Systems and Applications, 2,003
DOI, RIS, BibTex
H.-J. Stolberg,
M. Berekovic,
L. Friebe,
S. Moch,
M. B. Kulaczewski, and
P. Pirsch
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing
Very Large Scale Integration, 2,003
RIS, BibTex
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing
Very Large Scale Integration, 2,003
RIS, BibTex
H.-J. Stolberg,
M. Berekovic,
L. Friebe,
S. Moch,
S. Flügel,
M. B. Kulaczewski, and
P. Pirsch
HiBRID-SoC: a multi-core architecture for image and video applications
International Conference on Image Processing, 2,003
DOI, RIS, BibTex
HiBRID-SoC: a multi-core architecture for image and video applications
International Conference on Image Processing, 2,003
DOI, RIS, BibTex
H.-J. Stolberg,
M. Berekovic, and
P. Pirsch
A platform-independent methodology for performance estimation of streaming media applications
International Conference on Multimedia Computing and Systems/International Conference on Multimedia and Expo, 2,002
DOI, RIS, BibTex
A platform-independent methodology for performance estimation of streaming media applications
International Conference on Multimedia Computing and Systems/International Conference on Multimedia and Expo, 2,002
DOI, RIS, BibTex
M. Berekovic,
H.-J. Stolberg,
P. Pirsch, and
H. Runge
A programmable co-porcessor for MPEG-4 video
ICASSP '01: Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference, IEEE Computer Society, 2,001, ISBN 0-7803-7041-4
DOI, ISBN, RIS, BibTex
A programmable co-porcessor for MPEG-4 video
ICASSP '01: Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference, IEEE Computer Society, 2,001, ISBN 0-7803-7041-4
DOI, ISBN, RIS, BibTex
H.-J. Stolberg,
M. Berekovic,
P. Pirsch, and
H. Runge
The MPEG4 Advanced Simple profile - a complexity study
Workshop and Exhibition on Moving Picture Experts Group, 2,001
DOI, RIS, BibTex
The MPEG4 Advanced Simple profile - a complexity study
Workshop and Exhibition on Moving Picture Experts Group, 2,001
DOI, RIS, BibTex
H.-J. Stolberg,
M. Berekovic,
P. Pirsch, and
H. Runge
Implementing The MPEG4 Advanced Simple Profile For Streaming Video Applications
International Conference on Multimedia Computing and Systems/International Conference on Multimedia and Expo, 2,001
DOI, RIS, BibTex
Implementing The MPEG4 Advanced Simple Profile For Streaming Video Applications
International Conference on Multimedia Computing and Systems/International Conference on Multimedia and Expo, 2,001
DOI, RIS, BibTex
M. Berekovic,
P. Pirsch,
T. Selinger,
K. -.-.. Wels,
C. Miro,
A. Lafage,
C. Heer, and
G. Ghigo
Architecture of an Image Rendering Co-Processor for MPEG-4 Systems
ASAP '00: Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, IEEE Computer Society, 2,000, ISBN 0-7695-0716-6
ISBN, RIS, BibTex
Architecture of an Image Rendering Co-Processor for MPEG-4 Systems
ASAP '00: Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, IEEE Computer Society, 2,000, ISBN 0-7695-0716-6
ISBN, RIS, BibTex
C. Heer,
C. Miro,
A. Lafage,
M. Berekovic,
G. Ghigo,
T. Selinger, and
K.-I. Wels
Coprocessor architecture for MPEG4 video object rendering
Visual Communications and Image Processing, 2,000
RIS, BibTex
Coprocessor architecture for MPEG4 video object rendering
Visual Communications and Image Processing, 2,000
RIS, BibTex
M. Berekovic,
P. Pirsch,
T. Selinger,
K.-I. Wels,
C. Miro,
A. Lafage,
C. Heer, and
G. Ghigo
Coprocessor architecture for MPEG4 main profile visual compositing
IEEE International Symposium on Circuits and Systems, 2,000
DOI, RIS, BibTex
Coprocessor architecture for MPEG4 main profile visual compositing
IEEE International Symposium on Circuits and Systems, 2,000
DOI, RIS, BibTex
H.-J. Stolberg,
M. Berekovic,
P. Pirsch,
H. Runge,
H. Moller, and
J. Kneip
The M-PIRE MPEG4 codec DSP and its macroblock engine
IEEE International Symposium on Circuits and Systems, 2,000
DOI, RIS, BibTex
The M-PIRE MPEG4 codec DSP and its macroblock engine
IEEE International Symposium on Circuits and Systems, 2,000
DOI, RIS, BibTex
H. Kloos,
M. Berekovic, and
P. Pirsch
Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-Anwendungen
Architektur von Rechensystemen, Systemarchitektur auf dem Weg ins 3. Jahrtausend: Neue Strukturen, Konzepte, Verfahren und Bewertungsmethoden - Vorträge der 15. GI/ITG-Fachtagung ARCS '99 und der APS'99 (Arbeitsplatzrechensysteme), VDE-Verlag GmbH, 1,999, ISBN 3-8007-2482-0
ISBN, RIS, BibTex
Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-Anwendungen
Architektur von Rechensystemen, Systemarchitektur auf dem Weg ins 3. Jahrtausend: Neue Strukturen, Konzepte, Verfahren und Bewertungsmethoden - Vorträge der 15. GI/ITG-Fachtagung ARCS '99 und der APS'99 (Arbeitsplatzrechensysteme), VDE-Verlag GmbH, 1,999, ISBN 3-8007-2482-0
ISBN, RIS, BibTex
M. Berekovic,
T. Selinger,
C. Miro,
G. Ghigo,
C. Heer,
P. Pirsch,
K.-I. Wels, and
A. Lafage
The TANGRAM co-processor for MPEG4 visual compositing
IEEE Workshop on Signal Processing Systems, 1,999
DOI, RIS, BibTex
The TANGRAM co-processor for MPEG4 visual compositing
IEEE Workshop on Signal Processing Systems, 1,999
DOI, RIS, BibTex
M. Berekovic,
K. Jacob, and
P. Pirsch
Architecture of a hardware module for MPEG4 shape decoding
IEEE International Symposium on Circuits and Systems, 1,999
DOI, RIS, BibTex
Architecture of a hardware module for MPEG4 shape decoding
IEEE International Symposium on Circuits and Systems, 1,999
DOI, RIS, BibTex
M. Berekovic and
P. Pirsch
An Array Processor Architecture with Parallel Data Cache for Image Rendering and Compositing
CGI '98: Proceedings of the Computer Graphics International 1998, IEEE Computer Society, 1,998, ISBN 0-8186-8445-3
ISBN, RIS, BibTex
An Array Processor Architecture with Parallel Data Cache for Image Rendering and Compositing
CGI '98: Proceedings of the Computer Graphics International 1998, IEEE Computer Society, 1,998, ISBN 0-8186-8445-3
ISBN, RIS, BibTex
M. Berekovic,
R. Frase, and
P. Pirsch
A flexible processor architecture for MPEG4 image compositing
International Conference on Acoustics, Speech, and Signal Processing, 1,998
DOI, RIS, BibTex
A flexible processor architecture for MPEG4 image compositing
International Conference on Acoustics, Speech, and Signal Processing, 1,998
DOI, RIS, BibTex
M. Berekovic,
D. Heistermann, and
P. Pirsch
A core generator for fully synthesizable and highly parameterizable RISC-cores for system-on-chip designs
IEEE Workshop on Signal Processing Systems, 1,998
DOI, RIS, BibTex
A core generator for fully synthesizable and highly parameterizable RISC-cores for system-on-chip designs
IEEE Workshop on Signal Processing Systems, 1,998
DOI, RIS, BibTex
J. P. Wittenburg,
W. Hinrichs,
J. Kneip,
M. Ohmacht,
M. Berekovic,
H. Lieske,
H. Kloos, and
P. Pirsch
Realization of a programmable parallel DSP for high performance image processing applications
DAC '98: Proceedings of the 35th annual Design Automation Conference, ACM, 1,998, ISBN 0-89791-964-5
DOI, ISBN, RIS, BibTex
Realization of a programmable parallel DSP for high performance image processing applications
DAC '98: Proceedings of the 35th annual Design Automation Conference, ACM, 1,998, ISBN 0-89791-964-5
DOI, ISBN, RIS, BibTex
M. Berekovic,
H. Kloos, and
P. Pirsch
Hardware realization of a Java virtual machine for high performance multimedia applications
IEEE Workshop on Signal Processing Systems, 1,997
DOI, RIS, BibTex
Hardware realization of a Java virtual machine for high performance multimedia applications
IEEE Workshop on Signal Processing Systems, 1,997
DOI, RIS, BibTex
J. Kneip,
M. Berekovic, and
P. Pirsch
An algorithm-hardware-system approach to VLIW multimedia processors
Multimedia Signal Processing, 1,997
DOI, RIS, BibTex
An algorithm-hardware-system approach to VLIW multimedia processors
Multimedia Signal Processing, 1,997
DOI, RIS, BibTex
J. Kneip,
J. P. Wittenburg,
M. Berekovic,
K. Ronner, and
P. Pirsch
An algorithm adapted autonomous controlling concept for a parallel single-chip digital signal processor
Workshop on VLSI Signal Processing, 1,995
DOI, RIS, BibTex
An algorithm adapted autonomous controlling concept for a parallel single-chip digital signal processor
Workshop on VLSI Signal Processing, 1,995
DOI, RIS, BibTex
Books
J. Penders,
B. Gyselinckx,
R. Vullers,
O. Rousseaux,
M. Berekovic,
M. D. Nil,
C. V. Hoof,
J. Ryckaert,
et al.
Human++: Emerging Technology for Body Area Networks
2,008
DOI, RIS, BibTex
Human++: Emerging Technology for Body Area Networks
2,008
DOI, RIS, BibTex
M. Berekovic,
F. Bouwens,
T. V. Aa, and
D. Verkest
Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor
Workshop on Power and Timing Modeling, Optimization and Simulation, 2,008
DOI, RIS, BibTex
Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor
Workshop on Power and Timing Modeling, Optimization and Simulation, 2,008
DOI, RIS, BibTex
J. Govers,
J. Huisken,
M. Berekovic,
O. Rousseaux,
F. Bouwens,
M. D. Nil, and
J. L. V. Meerbergen
Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP
High Performance Embedded Architectures and Compilers, 2,008
DOI, RIS, BibTex
Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP
High Performance Embedded Architectures and Compilers, 2,008
DOI, RIS, BibTex
F. Bouwens,
M. Berekovic,
B. D. Sutter, and
G. Gaydadjiev
Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array
High Performance Embedded Architectures and Compilers, 2,008
DOI, RIS, BibTex
Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array
High Performance Embedded Architectures and Compilers, 2,008
DOI, RIS, BibTex
J. W. M. Jacobs,
L. V. Engelen,
J. Kuper,
G. J. M. Smit,
S. Vassiliadis,
M. Berekovic, and
T. D. Hamalainen
Image Quantisation on a Massively Parallel Embedded Processor
Systems, Architectures, Modeling, and Simulation, 2,007
DOI, RIS, BibTex
Image Quantisation on a Massively Parallel Embedded Processor
Systems, Architectures, Modeling, and Simulation, 2,007
DOI, RIS, BibTex
L. Yseboodt,
M. D. Nil,
J. Huisken,
M. Berekovic,
Q. Zhao,
F. Bouwens, and
J. L. V. Meerbergen
Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring
Systems, Architectures, Modeling, and Simulation, 2,007
DOI, RIS, BibTex
Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring
Systems, Architectures, Modeling, and Simulation, 2,007
DOI, RIS, BibTex
K. Wu,
A. Kanstein,
J. Madsen, and
M. Berekovic
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
Applied Reconfigurable Computing, 2,007
DOI, RIS, BibTex
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
Applied Reconfigurable Computing, 2,007
DOI, RIS, BibTex
F. Bouwens,
M. Berekovic,
A. Kanstein, and
G. Gaydadjiev
Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array
Applied Reconfigurable Computing, 2,007
DOI, RIS, BibTex
Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array
Applied Reconfigurable Computing, 2,007
DOI, RIS, BibTex
B. D. Sutter,
B. Mei,
A. Bartic,
T. V. Aa,
M. Berekovic,
J.-y. Mignolet,
K. Croes,
P. Coene,
et al.
Hardware and a Tool Chain for ADRES
Applied Reconfigurable Computing, 2,006
DOI, RIS, BibTex
Hardware and a Tool Chain for ADRES
Applied Reconfigurable Computing, 2,006
DOI, RIS, BibTex
M. Berekovic and
T. Niggemeier
A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme
Systems, Architectures, Modeling, and Simulation, 2,006
DOI, RIS, BibTex
A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme
Systems, Architectures, Modeling, and Simulation, 2,006
DOI, RIS, BibTex