Conference Papers
C. Blochwitz,
J. Wolff,
M. Berekovic,
D. Heinrich,
S. Groppe,
J. Joseph, and
P. T.
Hardware-Triplestore – a Hardware-centric Database for Semantic Web
International Conference on Field-Programmable Technology, 2018, 2.018
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Hardware-Triplestore – a Hardware-centric Database for Semantic Web
International Conference on Field-Programmable Technology, 2018, 2.018
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J. M. Joseph,
M. Mey,
K. Ehlers,
C. Blochwitz,
T. Winker, and
T. Pionteck
Design Space Exploration for a Hardware-accelerated Embedded Real-Time Pose Estimation using Vivado HLS
ReConFig 2017, 2017, 2.017
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Design Space Exploration for a Hardware-accelerated Embedded Real-Time Pose Estimation using Vivado HLS
ReConFig 2017, 2017, 2.017
RIS, BibTex
J. Joseph,
C. Blochwitz,
A. García-Ortiz, and
T. Pionteck
Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs
MICPRO 2460, 36–47, Elsevier, Amsterdam 2017, 2.017
URL, RIS, BibTex
Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs
MICPRO 2460, 36–47, Elsevier, Amsterdam 2017, 2.017
URL, RIS, BibTex
C. Blochwitz,
J. Wolff,
J. M. Joseph,
S. Werner,
D. Heinrich,
S. Groppe, and
T. Pionteck
Hardware-accelerated Radix-Tree based string sorting for Big Data applications
30TH INTERNATIONAL CONFERENCE ON ARCHITECTURE OF COMPUTING SYSTEMS, Wien, 47-58, Springer, Cham 2017, 2.017
URL, RIS, BibTex
Hardware-accelerated Radix-Tree based string sorting for Big Data applications
30TH INTERNATIONAL CONFERENCE ON ARCHITECTURE OF COMPUTING SYSTEMS, Wien, 47-58, Springer, Cham 2017, 2.017
URL, RIS, BibTex
C. Blochwitz,
R. Klink,
J. M. Joseph, and
T. Pionteck
Contentious Live-Tracing as Debugging Approach on FPGAs
To Appear: ReConFig 2017, IEEE, Cancun, Mexiko 2017, 2.017
RIS, BibTex
Contentious Live-Tracing as Debugging Approach on FPGAs
To Appear: ReConFig 2017, IEEE, Cancun, Mexiko 2017, 2.017
RIS, BibTex
J. M. Joseph,
T. Winker,
K. Ehlers,
C. Blochwitz, and
T. Pionteck
Hardware-Accelerated Pose Estimation for Embedded Systems using Vivado HLS
ReConFig, Cancun, Mexiko 2016, 2.016
URL, DOI, RIS, BibTex
Hardware-Accelerated Pose Estimation for Embedded Systems using Vivado HLS
ReConFig, Cancun, Mexiko 2016, 2.016
URL, DOI, RIS, BibTex
J. M. Joseph,
S. Wrieden,
C. Blochwitz,
A. García-Ortiz, and
T. Pionteck
A Simulation Environment for Design Space Exploration for Asymmetric 3D-Network-on-Chip
11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), Tallinn 2016, 2.016
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A Simulation Environment for Design Space Exploration for Asymmetric 3D-Network-on-Chip
11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), Tallinn 2016, 2.016
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J. Joseph,
C. Blochwitz, and
T. Pionteck
Adaptive Allocation of Default Router Paths in Network-on-Chips for Latency Reduction
2016 International Conference on High Performance Computing & Simulation (HPCS), Innsbruck 2016, 2.016
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Adaptive Allocation of Default Router Paths in Network-on-Chips for Latency Reduction
2016 International Conference on High Performance Computing & Simulation (HPCS), Innsbruck 2016, 2.016
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C. Blochwitz,
J. M. Joseph,
T. Pionteck,
R. Backasch,
S. Werner,
D. Heinrich, and
S. Groppen
An optimized Radix-Tree for hardware-accelerated index generation for Semantic Web Databases
To Appear: International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexiko 2015, 2.015
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An optimized Radix-Tree for hardware-accelerated index generation for Semantic Web Databases
To Appear: International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexiko 2015, 2.015
RIS, BibTex
J. M. Joseph and
T. Pionteck
A Cycle-Accurate Network-on-Chip Simulator with Support for Abstract Task Graph Modeling
Symposium on System-on-Chip (SOC), Tampere, Finland 2014, 2.014
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A Cycle-Accurate Network-on-Chip Simulator with Support for Abstract Task Graph Modeling
Symposium on System-on-Chip (SOC), Tampere, Finland 2014, 2.014
RIS, BibTex