Journal Articles
M. Berekovic and
T. Niggemeier
A distributed, simultaneously multi-threaded (SMT) processor with clustered scheduling windows for scalable DSP performance
J. Signal Process. Syst., 50(2), 2,008
DOI, RIS, BibTex
A distributed, simultaneously multi-threaded (SMT) processor with clustered scheduling windows for scalable DSP performance
J. Signal Process. Syst., 50(2), 2,008
DOI, RIS, BibTex
M. Berekovic and
T. Niggemeier
A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance
Journal of Signal Processing Systems, 50, 2,008
DOI, RIS, BibTex
A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance
Journal of Signal Processing Systems, 50, 2,008
DOI, RIS, BibTex
Conference Papers
M. Berekovic and
T. Niggemeier
A scalable, multi-thread, multi-issue array processor architecture for DSP applications based on extended tomasulo scheme
SAMOS'06: Proceedings of the 6th international conference on Embedded Computer Systems, Springer-Verlag, 2,006, ISBN 3-540-36410-2, 978-3-540-36410-8
DOI, ISBN, RIS, BibTex
A scalable, multi-thread, multi-issue array processor architecture for DSP applications based on extended tomasulo scheme
SAMOS'06: Proceedings of the 6th international conference on Embedded Computer Systems, Springer-Verlag, 2,006, ISBN 3-540-36410-2, 978-3-540-36410-8
DOI, ISBN, RIS, BibTex
Books
M. Berekovic and
T. Niggemeier
A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme
Systems, Architectures, Modeling, and Simulation, 2,006
DOI, RIS, BibTex
A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme
Systems, Architectures, Modeling, and Simulation, 2,006
DOI, RIS, BibTex