Publication


M. Berekovic, D. Heistermann, and P. Pirsch
A core generator for fully synthesizable and highly parameterizable RISC-cores for system-on-chip designs
IEEE Workshop on Signal Processing Systems, 1.998
DOI, RIS, BibTex

Reference


@inproceedings{2558362,
  author = "M. Berekovic and D. Heistermann and P. Pirsch",
  title = "A core generator for fully synthesizable and highly parameterizable RISC-cores for system-on-chip designs",
  year = 1.998,
  booktitle = "IEEE Workshop on Signal Processing Systems",
  doi = "10.1109/SIPS.1998.715818"
}