Journal Articles
D. Heinrich,
S. Werner,
C. Blochwitz,
T. Pionteck, and
S. Groppe
Hardware-aided update acceleration in a hybrid Semantic Web database system
The Journal of Supercomputing, 2020, 2,020
RIS, BibTex
Hardware-aided update acceleration in a hybrid Semantic Web database system
The Journal of Supercomputing, 2020, 2,020
RIS, BibTex
S. Werner,
D. Heinrich,
S. Groppe,
C. Blochwitz, and
T. Pionteck
Runtime Adaptive Hybrid Query Engine based on FPGAs
Open Journal of Databases (OJDB), 2016, 2,016
URL, RIS, BibTex
Runtime Adaptive Hybrid Query Engine based on FPGAs
Open Journal of Databases (OJDB), 2016, 2,016
URL, RIS, BibTex
S. Groppe,
D. Heinrich,
C. Blochwitz, and
T. Pionteck
Constructing Large-Scale Semantic Web Indices for the Six RDF Collation Orders
Open Journal of Big Data (OJBD), 2016, 2,016
URL, RIS, BibTex
Constructing Large-Scale Semantic Web Indices for the Six RDF Collation Orders
Open Journal of Big Data (OJBD), 2016, 2,016
URL, RIS, BibTex
S. Groppe,
D. Heinrich,
S. Werner,
C. Blochwitz, and
T. Pionteck
PatTrieSort - External String Sorting based on Patricia Tries
Open Journal of Databases (OJDB), 2015, 2,015
URL, RIS, BibTex
PatTrieSort - External String Sorting based on Patricia Tries
Open Journal of Databases (OJDB), 2015, 2,015
URL, RIS, BibTex
T. Pionteck
A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime
International Journal of Reconfigurable Computing, vol. 2009, Article ID 942930,, Hindawi Publishing Corporation, New York 2009, 2,009
URL, RIS, BibTex
A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime
International Journal of Reconfigurable Computing, vol. 2009, Article ID 942930,, Hindawi Publishing Corporation, New York 2009, 2,009
URL, RIS, BibTex
T. Pionteck,
C. Albrecht,
R.,
Koch,
E., and
Maehle
Adaptive Communication Architectures for Runtime Reconfigurable System-on-Chips
Parallel Processing Letters, 275-289, World Scientific Publishing, 2008, 2,008
URL, RIS, BibTex
Adaptive Communication Architectures for Runtime Reconfigurable System-on-Chips
Parallel Processing Letters, 275-289, World Scientific Publishing, 2008, 2,008
URL, RIS, BibTex
Conference Papers
J. M. Joseph,
M. Mey,
K. Ehlers,
C. Blochwitz,
T. Winker, and
T. Pionteck
Design Space Exploration for a Hardware-accelerated Embedded Real-Time Pose Estimation using Vivado HLS
ReConFig 2017, 2017, 2,017
RIS, BibTex
Design Space Exploration for a Hardware-accelerated Embedded Real-Time Pose Estimation using Vivado HLS
ReConFig 2017, 2017, 2,017
RIS, BibTex
J. Joseph,
C. Blochwitz,
A. García-Ortiz, and
T. Pionteck
Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs
MICPRO 2460, 36–47, Elsevier, Amsterdam 2017, 2,017
URL, RIS, BibTex
Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs
MICPRO 2460, 36–47, Elsevier, Amsterdam 2017, 2,017
URL, RIS, BibTex
C. Blochwitz,
J. Wolff,
J. M. Joseph,
S. Werner,
D. Heinrich,
S. Groppe, and
T. Pionteck
Hardware-accelerated Radix-Tree based string sorting for Big Data applications
30TH INTERNATIONAL CONFERENCE ON ARCHITECTURE OF COMPUTING SYSTEMS, Wien, 47-58, Springer, Cham 2017, 2,017
URL, RIS, BibTex
Hardware-accelerated Radix-Tree based string sorting for Big Data applications
30TH INTERNATIONAL CONFERENCE ON ARCHITECTURE OF COMPUTING SYSTEMS, Wien, 47-58, Springer, Cham 2017, 2,017
URL, RIS, BibTex
C. Blochwitz,
R. Klink,
J. M. Joseph, and
T. Pionteck
Contentious Live-Tracing as Debugging Approach on FPGAs
To Appear: ReConFig 2017, IEEE, Cancun, Mexiko 2017, 2,017
RIS, BibTex
Contentious Live-Tracing as Debugging Approach on FPGAs
To Appear: ReConFig 2017, IEEE, Cancun, Mexiko 2017, 2,017
RIS, BibTex
J. M. Joseph,
T. Winker,
K. Ehlers,
C. Blochwitz, and
T. Pionteck
Hardware-Accelerated Pose Estimation for Embedded Systems using Vivado HLS
ReConFig, Cancun, Mexiko 2016, 2,016
URL, DOI, RIS, BibTex
Hardware-Accelerated Pose Estimation for Embedded Systems using Vivado HLS
ReConFig, Cancun, Mexiko 2016, 2,016
URL, DOI, RIS, BibTex
J. M. Joseph,
S. Wrieden,
C. Blochwitz,
A. García-Ortiz, and
T. Pionteck
A Simulation Environment for Design Space Exploration for Asymmetric 3D-Network-on-Chip
11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), Tallinn 2016, 2,016
URL, DOI, RIS, BibTex
A Simulation Environment for Design Space Exploration for Asymmetric 3D-Network-on-Chip
11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), Tallinn 2016, 2,016
URL, DOI, RIS, BibTex
J. Joseph,
C. Blochwitz, and
T. Pionteck
Adaptive Allocation of Default Router Paths in Network-on-Chips for Latency Reduction
2016 International Conference on High Performance Computing & Simulation (HPCS), Innsbruck 2016, 2,016
URL, RIS, BibTex
Adaptive Allocation of Default Router Paths in Network-on-Chips for Latency Reduction
2016 International Conference on High Performance Computing & Simulation (HPCS), Innsbruck 2016, 2,016
URL, RIS, BibTex
S. Werner,
D. Heinrich,
M. Stelzner,
V. Linnemann,
T. Pionteck, and
S. Groppe
Accelerated join evaluation in Semantic Web databases by using FPGAs
Concurrency and Computation: Practice and Experience, Wiley, 2015, 2,015
URL, DOI, RIS, BibTex
Accelerated join evaluation in Semantic Web databases by using FPGAs
Concurrency and Computation: Practice and Experience, Wiley, 2015, 2,015
URL, DOI, RIS, BibTex
S. Werner,
D. Heinrich,
J. Piper,
S. Groppe,
R. Backasch,
C. Blochwitz, and
T. Pionteck
Automated Composition and Execution of Hardware-accelerated Operator Graphs
To Appear: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), IEEE, Bremen 2015, 2,015
RIS, BibTex
Automated Composition and Execution of Hardware-accelerated Operator Graphs
To Appear: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), IEEE, Bremen 2015, 2,015
RIS, BibTex
D. Heinrich,
S. Werner,
M. Stelzner,
C. Blochwitz,
T. Pionteck, and
S. Groppe
Hybrid FPGA Approach for a B+ Tree in a Semantic Web Database System
To Appear: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), IEEE, Bremen 2015, 2,015
RIS, BibTex
Hybrid FPGA Approach for a B+ Tree in a Semantic Web Database System
To Appear: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), IEEE, Bremen 2015, 2,015
RIS, BibTex
C. Blochwitz,
J. M. Joseph,
T. Pionteck,
R. Backasch,
S. Werner,
D. Heinrich, and
S. Groppen
An optimized Radix-Tree for hardware-accelerated index generation for Semantic Web Databases
To Appear: International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexiko 2015, 2,015
RIS, BibTex
An optimized Radix-Tree for hardware-accelerated index generation for Semantic Web Databases
To Appear: International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexiko 2015, 2,015
RIS, BibTex
R. Backasch,
G. Hempel,
T. Pionteck,
S. Groppe, and
S. Werner
An Architectural Template for Composing Application Specific Datapaths at Runtime
To Appear: International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexiko 2015, 2,015
RIS, BibTex
An Architectural Template for Composing Application Specific Datapaths at Runtime
To Appear: International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexiko 2015, 2,015
RIS, BibTex
S. Werner,
D. Heinrich,
M. Stelzner,
S. Groppe,
R. Backasch, and
T. Pionteck
Parallel and Pipelined Filter Operator for Hardware-Accelerated Operator Graphs in Semantic Web Databases
14th IEEE International Conference on Computer and Information Technology (CIT2014), IEEE, Xi´an, China 2014, 2,014
RIS, BibTex
Parallel and Pipelined Filter Operator for Hardware-Accelerated Operator Graphs in Semantic Web Databases
14th IEEE International Conference on Computer and Information Technology (CIT2014), IEEE, Xi´an, China 2014, 2,014
RIS, BibTex
M. Raitza,
M. Vogt,
C. Hochberger, and
T. Pionteck
Influence of Magnetic Fields and X-Radiation on Ring Oscillators in FPGAs
21th Reconfigurable Architecture Workshop (RAW), IEEE, Phoenix, USA 2014, 2,014
RIS, BibTex
Influence of Magnetic Fields and X-Radiation on Ring Oscillators in FPGAs
21th Reconfigurable Architecture Workshop (RAW), IEEE, Phoenix, USA 2014, 2,014
RIS, BibTex
J. M. Joseph and
T. Pionteck
A Cycle-Accurate Network-on-Chip Simulator with Support for Abstract Task Graph Modeling
Symposium on System-on-Chip (SOC), Tampere, Finland 2014, 2,014
RIS, BibTex
A Cycle-Accurate Network-on-Chip Simulator with Support for Abstract Task Graph Modeling
Symposium on System-on-Chip (SOC), Tampere, Finland 2014, 2,014
RIS, BibTex
R. Backasch,
G. Hempel,
S. Groppe,
S. Werner, and
T. Pionteck
Identifying Homogenous Reconfigurable Regions in Heterogeneous FPGAs for Module Relocation
International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1-6, IEEE, Cancun, Mexiko 2014, 2,014
URL, DOI, RIS, BibTex
Identifying Homogenous Reconfigurable Regions in Heterogeneous FPGAs for Module Relocation
International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1-6, IEEE, Cancun, Mexiko 2014, 2,014
URL, DOI, RIS, BibTex
S. Werner,
S. Groppe,
V. Linnemann, and
T. Pionteck
Hardware-accelerated Join Processing in Large Semantic Web Databases with FPGas
International Conference on High Performance Computing and Simulation (HPCS), 131 - 138, IEEE, Helsinki, Finland 2013, 2,013
RIS, BibTex
Hardware-accelerated Join Processing in Large Semantic Web Databases with FPGas
International Conference on High Performance Computing and Simulation (HPCS), 131 - 138, IEEE, Helsinki, Finland 2013, 2,013
RIS, BibTex
T. Pionteck and
C. Osterloh
Prioritizing Semi-Static Data Streams in Network-on-Chips for Runtime Reconfigurable Systems
Interantional Workshop on Dynamic Reconfigurable Network-on-Chip (DRNoC), 229 - 232, IEEE, Helsinki, Finland 2013, 2,013
RIS, BibTex
Prioritizing Semi-Static Data Streams in Network-on-Chips for Runtime Reconfigurable Systems
Interantional Workshop on Dynamic Reconfigurable Network-on-Chip (DRNoC), 229 - 232, IEEE, Helsinki, Finland 2013, 2,013
RIS, BibTex
G. Hempel,
J. Hoyer,
T. Pionteck, and
C. Hochberger
Register Allocation for High-Level Synthesis of Hardware Accelerators Targeting FPGAs
8th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 1 - 6, IEEE, Darmstadt, Germany 2013, 2,013
RIS, BibTex
Register Allocation for High-Level Synthesis of Hardware Accelerators Targeting FPGAs
8th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 1 - 6, IEEE, Darmstadt, Germany 2013, 2,013
RIS, BibTex
T. Pionteck and
C. Osterloh
Notion of Time and Parallelism: What Computer Science Students need to know about Digital Circuit Design
9th European Workshop on Microelectronic, 48-50, EDA Publishing, 2012, 2,012
URL, RIS, BibTex
Notion of Time and Parallelism: What Computer Science Students need to know about Digital Circuit Design
9th European Workshop on Microelectronic, 48-50, EDA Publishing, 2012, 2,012
URL, RIS, BibTex
C. Osterloh,
T. Pionteck, and
E. Maehle
MONSUN II: A small and inexpensive AUV for underwater swarms
7th German Conference on Robotics (ROBOTIK 2012), 325-330, München 2012, 2,012
URL, RIS, BibTex
MONSUN II: A small and inexpensive AUV for underwater swarms
7th German Conference on Robotics (ROBOTIK 2012), 325-330, München 2012, 2,012
URL, RIS, BibTex
C. Osterloh,
B. Meyer,
A. Amory,
T. Pionteck, and
E. Maehle
MONSUN II - Towards Autonomous Underwater Swarms for Environmental Monitoring
IROS2012 - Workshop on Robotics for Environmental Monitoring, 1-6, Vilamoura, Algarve, Portugal 2012, 2,012
URL, RIS, BibTex
MONSUN II - Towards Autonomous Underwater Swarms for Environmental Monitoring
IROS2012 - Workshop on Robotics for Environmental Monitoring, 1-6, Vilamoura, Algarve, Portugal 2012, 2,012
URL, RIS, BibTex
V. Hampel,
T. Pionteck, and
E. Maehle
An Approach for Performance Estimation of Hybrid Systems with FPGAs and GPUs as Coprocessors
25th International Conference on Architecture of Computing Systems (ARCS) 2012, 160-171, Springer, 2012, 2,012
URL, RIS, BibTex
An Approach for Performance Estimation of Hybrid Systems with FPGAs and GPUs as Coprocessors
25th International Conference on Architecture of Computing Systems (ARCS) 2012, 160-171, Springer, 2012, 2,012
URL, RIS, BibTex
T. Pionteck,
C. Osterloh, and
C. Albrecht
Linking Formal Description and Simulation of Runtime Reconfigurable Systems
International Conference on Reconfigurable Computing and FPGAs (ReConFig), 158-164, 2011, 2,011
URL, DOI, RIS, BibTex
Linking Formal Description and Simulation of Runtime Reconfigurable Systems
International Conference on Reconfigurable Computing and FPGAs (ReConFig), 158-164, 2011, 2,011
URL, DOI, RIS, BibTex
R. Maas,
T. Pionteck, and
E. Maehle
Wave front-based Colour Reduction for Colour Segmentation
Biomed Tech 2011; 56 (Suppl. 1); ISSN 0939-4990 DOI 10.1515/BMT.2011.578, Walter de Gruyter, Freiburg 2011, 2,011
RIS, BibTex
Wave front-based Colour Reduction for Colour Segmentation
Biomed Tech 2011; 56 (Suppl. 1); ISSN 0939-4990 DOI 10.1515/BMT.2011.578, Walter de Gruyter, Freiburg 2011, 2,011
RIS, BibTex
T. Pionteck,
S. Sammann, and
C. Albrecht
Optimizing Runtime Reconfiguration Decisions
International Conference on Embedded and Ubiquitous Computing (EUC), 39-46, IEEE Computer Society, 2010, 2,010
URL, DOI, RIS, BibTex
Optimizing Runtime Reconfiguration Decisions
International Conference on Embedded and Ubiquitous Computing (EUC), 39-46, IEEE Computer Society, 2010, 2,010
URL, DOI, RIS, BibTex
T. Pionteck,
C. Osterloh, and
C. Albrecht
Latency Reduction of Selected Data Streams in Network-on-Chips for Adaptive Manycore Systems
28th IEEE Norchip Conference, 1-6, Tampere/Finnland 2010, 2,010
RIS, BibTex
Latency Reduction of Selected Data Streams in Network-on-Chips for Adaptive Manycore Systems
28th IEEE Norchip Conference, 1-6, Tampere/Finnland 2010, 2,010
RIS, BibTex
T. Pionteck and
W. Brockmann
A Concept of a Trust Management Architecture to Increase the Robustness of Nano Age Devices
4th Workshop on Dependable and Secure Nanocomputing (in conjunction with the 40th Annual IEEE/IFIP Int. Conf. on Dependable Systems and Networks - DSN-2010), 142-147, 2010, 2,010
RIS, BibTex
A Concept of a Trust Management Architecture to Increase the Robustness of Nano Age Devices
4th Workshop on Dependable and Secure Nanocomputing (in conjunction with the 40th Annual IEEE/IFIP Int. Conf. on Dependable Systems and Networks - DSN-2010), 142-147, 2010, 2,010
RIS, BibTex
R. Koch,
C. Albrecht, and
T. Pionteck
Adaptive Health Monitoring in a Reconfigurable Network-on-Chip
Workshop on Diagnostic Services in Network-on-Chips (DSNOC), Nice 2009, 2,009
RIS, BibTex
Adaptive Health Monitoring in a Reconfigurable Network-on-Chip
Workshop on Diagnostic Services in Network-on-Chips (DSNOC), Nice 2009, 2,009
RIS, BibTex
C. Albrecht,
R. Koch, and
T. Pionteck
On the Impact of Buffer Size on Packet Loss in Adaptable Network-on-Chips for Runtime Reconfigurable System-on-Chips
NORCHIP, 1-4, Trondheim 2009, 2,009
URL, RIS, BibTex
On the Impact of Buffer Size on Packet Loss in Adaptable Network-on-Chips for Runtime Reconfigurable System-on-Chips
NORCHIP, 1-4, Trondheim 2009, 2,009
URL, RIS, BibTex
C. Albrecht,
R. Koch,
T. Pionteck, and
P. Glösekötter
Towards a Flexible Fault-Tolerant System-on-Chip
22th International Conference on Architecture of Computing Systems - Workshop Proceedings, 83-90, VDE Verlag GmbH, Berlin 2009, 2,009
URL, RIS, BibTex
Towards a Flexible Fault-Tolerant System-on-Chip
22th International Conference on Architecture of Computing Systems - Workshop Proceedings, 83-90, VDE Verlag GmbH, Berlin 2009, 2,009
URL, RIS, BibTex
C. Albrecht,
J. Foag,
R. Koch,
E. Maehle, and
T. Pionteck
DynaCORE – Dynamically Reconfigurable Coprocessor for Network Processors
Dynamically Reconfigurable Systems Architectures: Design Methods and Applications, Springer, 2009, 2,009
URL, RIS, BibTex
DynaCORE – Dynamically Reconfigurable Coprocessor for Network Processors
Dynamically Reconfigurable Systems Architectures: Design Methods and Applications, Springer, 2009, 2,009
URL, RIS, BibTex
T. Pionteck,
R. Koch,
C. Albrecht,
E. Maehle,
M. Meitinger,
R. Ohlendorf,
T. Wild, and
A. Herkersdorf
SPP1148 booth: Network processors
International Conference on Field Programmable Logic and Applications, 352, IEEE, Heidelberg 2008, 2,008
URL, RIS, BibTex
SPP1148 booth: Network processors
International Conference on Field Programmable Logic and Applications, 352, IEEE, Heidelberg 2008, 2,008
URL, RIS, BibTex
T. Pionteck,
C. Albrecht,
R. Koch, and
E. Maehle
ON THE DESIGN PARAMETERS OF RUNTIME RECONFIGURABLE SYSTEMS
International Conference on Field Programmable Logic and Applications, 683-686, IEEE, Heidelberg 2008, 2,008
URL, RIS, BibTex
ON THE DESIGN PARAMETERS OF RUNTIME RECONFIGURABLE SYSTEMS
International Conference on Field Programmable Logic and Applications, 683-686, IEEE, Heidelberg 2008, 2,008
URL, RIS, BibTex
T. Pionteck,
C. Albrecht,
R. Koch, and
E. Maehle
Performance and Reliability Monitoring in Network-on-Chips
Workshop on Diagnostic Services in Network-on-Chips (DSNOC), 2008, 2,008
URL, RIS, BibTex
Performance and Reliability Monitoring in Network-on-Chips
Workshop on Diagnostic Services in Network-on-Chips (DSNOC), 2008, 2,008
URL, RIS, BibTex
T. Pionteck,
C. Albrecht,
R. Koch,
T. Brix, and
E. Maehle
Design and Simulation of Runtime Reconfigurable Systems
IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2008 ), 154-157, IEEE, 2008, 2,008
RIS, BibTex
Design and Simulation of Runtime Reconfigurable Systems
IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2008 ), 154-157, IEEE, 2008, 2,008
RIS, BibTex
C. Albrecht,
M. Werner,
T. Pionteck,
R. Fuchsen,
R. Koch, and
E. Maehle
WCET Determination Tool for Embedded Systems Software
SIMUTools08 Proceedings, 1, ICST, Marseille, France 2008, 2,008
URL, RIS, BibTex
WCET Determination Tool for Embedded Systems Software
SIMUTools08 Proceedings, 1, ICST, Marseille, France 2008, 2,008
URL, RIS, BibTex
C. Albrecht,
P. Roß,
R. Koch,
T. Pionteck, and
E. Maehle
Performance Analysis of Bus-Based Interconnects for a Run-Time Reconfigurable Co-Processor Platform
PDP 08, 200-205, IEEE Computer Society, Toulouse, France 2008, 2,008
URL, DOI, RIS, BibTex
Performance Analysis of Bus-Based Interconnects for a Run-Time Reconfigurable Co-Processor Platform
PDP 08, 200-205, IEEE Computer Society, Toulouse, France 2008, 2,008
URL, DOI, RIS, BibTex
C. Albrecht,
C. Osterloh,
T. Pionteck,
R. Koch, and
E. Maehle
An Application-Oriented Synthetic Network Traffic Generator
European Conference on Modelling and Simulation 2008, 299-305, ECMS, Nicosia, Cyprus 2008, 2,008
RIS, BibTex
An Application-Oriented Synthetic Network Traffic Generator
European Conference on Modelling and Simulation 2008, 299-305, ECMS, Nicosia, Cyprus 2008, 2,008
RIS, BibTex
T. Pionteck,
S. Stiefmeier,
S. Staake, and
M. Glesner
On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction
VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), 283-297, Springer, 2007, 2,007
URL, RIS, BibTex
On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction
VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), 283-297, Springer, 2007, 2,007
URL, RIS, BibTex
T. Pionteck
Teaching Informatics Students the Secrets of Hardware Design
IEEE International Conference on Microelectronic Systems Education, 31 - 32, San Diego, USA 2007, 2,007
URL, RIS, BibTex
Teaching Informatics Students the Secrets of Hardware Design
IEEE International Conference on Microelectronic Systems Education, 31 - 32, San Diego, USA 2007, 2,007
URL, RIS, BibTex
T. Pionteck,
C. Albrecht,
R. Koch,
E. Maehle,
M. Hübner, and
J. Becker
Communication Architectures for Dynamically Reconfigurable FPGA Designs
14th Reconfigurable Architectures Workshop, 162, IEEE Computer Society, Long Beach, USA 2007, 2,007
URL, RIS, BibTex
Communication Architectures for Dynamically Reconfigurable FPGA Designs
14th Reconfigurable Architectures Workshop, 162, IEEE Computer Society, Long Beach, USA 2007, 2,007
URL, RIS, BibTex
R. Koch,
T. Pionteck,
C. Albrecht, and
E. Maehle
A Lightweight Framework for Runtime Reconfigurable System Prototyping
18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP 2007), 61-64, IEEE Computer Society, Porto Alegre, Brazil 2007, 2,007
RIS, BibTex
A Lightweight Framework for Runtime Reconfigurable System Prototyping
18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP 2007), 61-64, IEEE Computer Society, Porto Alegre, Brazil 2007, 2,007
RIS, BibTex
H. Hinkelmann,
P. Zipf,
M. Glesner, and
T. Pionteck
Dynamically Reconfigurable Computing for Wireless Communication Systems
IT-Magazin 3/2007, 174-180, Oldenbourg Wissenschaftsverlag, 2007, 2,007
URL, DOI, RIS, BibTex
Dynamically Reconfigurable Computing for Wireless Communication Systems
IT-Magazin 3/2007, 174-180, Oldenbourg Wissenschaftsverlag, 2007, 2,007
URL, DOI, RIS, BibTex
C. Albrecht,
T. Pionteck,
R. Koch, and
E. Maehle
Modelling Tile-Based Run-Time Reconfigurable Systems Using SystemC
European Conference on Modelling and Simulation 2007, 509-514, ISBN 978-0-9553018-2-7, Prague, Czech Republic 2007, 2,007
URL, RIS, BibTex
Modelling Tile-Based Run-Time Reconfigurable Systems Using SystemC
European Conference on Modelling and Simulation 2007, 509-514, ISBN 978-0-9553018-2-7, Prague, Czech Republic 2007, 2,007
URL, RIS, BibTex
C. Albrecht,
R. Koch,
T. Pionteck, and
E. Maehle
Simulation System for Run-Time Reconfigurable Networks-on-Chip
Proceedings of the 6th EUROSIM Congress on Modelling and Simulation, ARGESIM - ARGE Simulation News, Wiedner Hauptstrasse 8-10, 1040 Vienna 2007, 2,007
RIS, BibTex
Simulation System for Run-Time Reconfigurable Networks-on-Chip
Proceedings of the 6th EUROSIM Congress on Modelling and Simulation, ARGESIM - ARGE Simulation News, Wiedner Hauptstrasse 8-10, 1040 Vienna 2007, 2,007
RIS, BibTex
P. Zipf,
V. Hampel,
M. Glesner, and
T. Pionteck
Eine Scheduling Heuristik zur Minimierung der Verlustleistung
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 51-60, Dresden 2006, 2,006
RIS, BibTex
Eine Scheduling Heuristik zur Minimierung der Verlustleistung
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 51-60, Dresden 2006, 2,006
RIS, BibTex
T. Pionteck,
R. Koch, and
C. Albrecht
Applying Partial Reconfiguration to Networks-on-Chips
16th International Conference on Field Programmable Logic and Applications (FPL), 155-160, IEEE, Madrid, Spain 2006, 2,006
RIS, BibTex
Applying Partial Reconfiguration to Networks-on-Chips
16th International Conference on Field Programmable Logic and Applications (FPL), 155-160, IEEE, Madrid, Spain 2006, 2,006
RIS, BibTex
T. Pionteck,
C. Albrecht, and
R. Koch
A Dynamically Reconfigurable Packet-Switched Network-on-Chip
Design Automation and Test in Europe, Date 2006, 136-137, ACM SIGDA, München 2006, 2,006
RIS, BibTex
A Dynamically Reconfigurable Packet-Switched Network-on-Chip
Design Automation and Test in Europe, Date 2006, 136-137, ACM SIGDA, München 2006, 2,006
RIS, BibTex
R. Koch,
T. Pionteck,
C. Albrecht, and
E. Maehle
An Adaptive System-on-Chip for Network Applications
13th Reconfigurable Architectures Workshop (RAW 2006 ) associated with the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), IEEE, Rhodes Island, Greece 2006, 2,006
RIS, BibTex
An Adaptive System-on-Chip for Network Applications
13th Reconfigurable Architectures Workshop (RAW 2006 ) associated with the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), IEEE, Rhodes Island, Greece 2006, 2,006
RIS, BibTex
C. Albrecht,
R. Koch, and
T. Pionteck
On the Design of a Loosely-Coupled Run-Time Reconfigurable Network Coprocessor
Workshop on Media and Streaming Processors, 43-49, Barcelona, Spain 2005, 2,005
RIS, BibTex
On the Design of a Loosely-Coupled Run-Time Reconfigurable Network Coprocessor
Workshop on Media and Streaming Processors, 43-49, Barcelona, Spain 2005, 2,005
RIS, BibTex