Conference Papers
V. Hampel,
T. Pionteck, and
E. Maehle
An Approach for Performance Estimation of Hybrid Systems with FPGAs and GPUs as Coprocessors
25th International Conference on Architecture of Computing Systems (ARCS) 2012, 160-171, Springer, 2012, 2,012
URL, RIS, BibTex
An Approach for Performance Estimation of Hybrid Systems with FPGAs and GPUs as Coprocessors
25th International Conference on Architecture of Computing Systems (ARCS) 2012, 160-171, Springer, 2012, 2,012
URL, RIS, BibTex
V. Hampel,
G. Goronzy, and
E. Maehle
A Code-Based Analytical Approach for Using Separate Device Coprocessors in Computing Systems
24th International Conference on Architecture of Computing Systems (ARCS) 2011, BEST PAPER AWARD, 1-12, Springer-Verlag, Berlin/Heidelberg 2011, 2,011
URL, DOI, RIS, BibTex
A Code-Based Analytical Approach for Using Separate Device Coprocessors in Computing Systems
24th International Conference on Architecture of Computing Systems (ARCS) 2011, BEST PAPER AWARD, 1-12, Springer-Verlag, Berlin/Heidelberg 2011, 2,011
URL, DOI, RIS, BibTex
V. Hampel and
E. Maehle
A SSE-Based Implementation of a Ray Tracer for the Comparision with Coprocessors in Hybrid Computing Systems
24th PARS - Workshop on Parallel Systems and Algorithms, 131-140, Rüschlikon, Schweiz 2011, 2,011
URL, RIS, BibTex
A SSE-Based Implementation of a Ray Tracer for the Comparision with Coprocessors in Hybrid Computing Systems
24th PARS - Workshop on Parallel Systems and Algorithms, 131-140, Rüschlikon, Schweiz 2011, 2,011
URL, RIS, BibTex
V. Hampel and
E. Maehle
High-Level Application Design for Hybrid Computing Systems
23rd PARS-Workshop on Parallel Systems and Algorithms, 113-119, VDE Verlag GmbH, Berlin und Offenbach 2010, 2,010
RIS, BibTex
High-Level Application Design for Hybrid Computing Systems
23rd PARS-Workshop on Parallel Systems and Algorithms, 113-119, VDE Verlag GmbH, Berlin und Offenbach 2010, 2,010
RIS, BibTex
V. Hampel,
P. Sobe, and
E. Maehle
Experiences with a FPGA-based Reed/Solomon-encoding coprocessor
Microprocessors and Microsystems 32, 313-320, Elsevier, Amsterdam, The Netherlands 2008, 2,008
URL, DOI, RIS, BibTex
Experiences with a FPGA-based Reed/Solomon-encoding coprocessor
Microprocessors and Microsystems 32, 313-320, Elsevier, Amsterdam, The Netherlands 2008, 2,008
URL, DOI, RIS, BibTex
V. Hampel,
P. Sobe, and
E. Maehle
Designing Coprocessors for Hybrid Compute Systems
Reconfigurable Architectures Workshop, CD-ROM, IEEE Computer Society, Miami, Florida, USA 2008, 2,008
RIS, BibTex
Designing Coprocessors for Hybrid Compute Systems
Reconfigurable Architectures Workshop, CD-ROM, IEEE Computer Society, Miami, Florida, USA 2008, 2,008
RIS, BibTex
P. Sobe and
V. Hampel
FPGA-Accelerated Deletion-tolerant Coding for Reliable Distributed Storage
ARCS 2007 Proceedings, LNCS 4415, 14-27, Springer, Berlin. Heidelberg 2007, 2,007
RIS, BibTex
FPGA-Accelerated Deletion-tolerant Coding for Reliable Distributed Storage
ARCS 2007 Proceedings, LNCS 4415, 14-27, Springer, Berlin. Heidelberg 2007, 2,007
RIS, BibTex
V. Hampel,
P. Sobe, and
E. Maehle
Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor
10th Euromicro International Conference on Digital System Design, 77, IEEE Computer Society Press, Lübeck, Germany 2007, 2,007
URL, DOI, RIS, BibTex
Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor
10th Euromicro International Conference on Digital System Design, 77, IEEE Computer Society Press, Lübeck, Germany 2007, 2,007
URL, DOI, RIS, BibTex
P. Zipf,
V. Hampel,
M. Glesner, and
T. Pionteck
Eine Scheduling Heuristik zur Minimierung der Verlustleistung
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 51-60, Dresden 2006, 2,006
RIS, BibTex
Eine Scheduling Heuristik zur Minimierung der Verlustleistung
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 51-60, Dresden 2006, 2,006
RIS, BibTex