S. Werner, D. Heinrich, J. Piper, S. Groppe, R. Backasch, C. Blochwitz, and T. Pionteck
Automated Composition and Execution of Hardware-accelerated Operator Graphs
To Appear: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), IEEE, Bremen 2015, 2.015
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C. Blochwitz, J. M. Joseph, T. Pionteck, R. Backasch, S. Werner, D. Heinrich, and S. Groppen
An optimized Radix-Tree for hardware-accelerated index generation for Semantic Web Databases
To Appear: International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexiko 2015, 2.015
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R. Backasch, G. Hempel, T. Pionteck, S. Groppe, and S. Werner
An Architectural Template for Composing Application Specific Datapaths at Runtime
To Appear: International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexiko 2015, 2.015
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S. Werner, D. Heinrich, M. Stelzner, S. Groppe, R. Backasch, and T. Pionteck
Parallel and Pipelined Filter Operator for Hardware-Accelerated Operator Graphs in Semantic Web Databases
14th IEEE International Conference on Computer and Information Technology (CIT2014), IEEE, Xi´an, China 2014, 2.014
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R. Backasch, G. Hempel, S. Groppe, S. Werner, and T. Pionteck
Identifying Homogenous Reconfigurable Regions in Heterogeneous FPGAs for Module Relocation
International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1-6, IEEE, Cancun, Mexiko 2014, 2.014
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