A chip on a green circuit board
A processor on a circuit board

Research group

Secure Computing

Security that starts in the hardware. Embedded systems control vehicles, industrial plants and communication networks, and they must withstand attacks. We make microprocessors and AI accelerators secure.

What we work on

  • Secure processors based on open RISC-V architectures
  • Cryptographic accelerators, including computing on encrypted data
  • Hardware roots of trust and unique device identities
  • Finding and fixing security bugs in processors and neural-network accelerators

Trustworthy computing systems

We work on hardware security and on security solutions anchored in hardware:

  • a secure processor architecture based on open-source RISC-V
  • trustworthy AI accelerators
  • secure cryptographic accelerators and engines, including post-quantum cryptography
  • accelerators for homomorphic encryption, that is, computing on encrypted data
  • hardware roots of trust based on OpenTitan
  • implementing and evaluating the trustworthiness of systems-on-chip, and threat models for embedded devices

Design for hardware trust

A modern chip is made along a supply chain with many vendors and suppliers, not all of them trusted. In any phase someone can interfere and so harm the reliability and security of the chip. Against this we work on:

  • detecting hardware Trojans with machine learning and with process-specific functions
  • formal verification of Trojan-free, trusted circuits
  • protection against reverse engineering, counterfeiting and cloning, for example with physical unclonable functions (PUFs)
  • watermarking hardware IP at the level of physical design

One result is ML-Based Trojan Classification: Repercussions of Toxic Boundary Nets (IEEE Embedded Systems Letters, 2024).

From our research

  • Single engine architecture for hardware root of trust, Journal of Cryptographic Engineering, 2025
  • SCA-WAL: An Open-Source Framework for Power Side Channel Assessment at RTL and Netlist Level, IEEE Embedded Systems Letters, 2025
  • Optimizing Systolic Array-Based NTT Accelerators, IEEE Embedded Systems Letters, 2025
  • Lightweight Authenticated Integration and In-Field Secure Operation of System-in-Package, ACM Transactions on Design Automation of Electronic Systems, 2025

The group is led by Dr.-Ing. Saleh Mulhem; thesis topics are on his page.

Completed projects

Team