My research centers on pre-silicon hardware security, with particular emphasis on detecting and explaining power side-channel leakage at the register-transfer level (RTL) and netlist level prior to chip fabrication. Additionally, I investigate system-level modeling using SystemC and Transaction-Level Modeling (TLM) for AI accelerators, as well as hardware and deep neural network (DNN) co-design for embedded and RISC-V-based systems. I am a member of the Secure Computing group, collaborating with Dr. Saleh Mulhem.

Open Thesis Topics (BA/MA)

I’m happy to supervise bachelor and master theses in these areas:

• Pre-silicon power side-channel analysis
• Virtual prototypes (SystemC/TLM) of RISCV-Based System-On-Chip
• Hardware/DNN co-design and RISC-V extensions for edge AI
• Hardware/Software co-design for RISC-V cryptograhpic processors

Open-Source Projects

• SPARC-SCA (GitHub): Framework for root-cause analysis of power side-channel leakage in RISC-V processors, combining cell-level information flow tracking with signal-switching analysis. Evaluated on Ibex, Proteus, and Rocket running AES and Kyber (artifact of our ICCAD 2026 paper).
• SCA-WAL (GitHub): Extension of the Waveform Analysis Language (WAL) with Hamming-weight and Hamming-distance analysis across all signals, enabling power side-channel assessment directly from RTL and netlist simulation waveforms.

Since July 2021:

Research assistant at the Institute of Computer Engineering, University of Lübeck, Germany

April 2019 - March 2021:

M.Sc. Informational Technology/Computer Engineering, University of Rostock, Germany

October 2015 - March 2019:

B.Sc. Informational Technology/Computer Engineering, University of Rostock, Germany