DI-OSVISE

Anyone who designs a chip has to check that it does what it should. This verification today mostly needs expensive proprietary tools. DI-OSVISE (open-source design tools for the verification of processors and digital circuits) closes the gaps that remain when chips are designed with open-source tools, with a focus on instruction set extensions for RISC-V processors.

• Functional verification, sped up by co-simulation and a formal specification of the instruction set extensions
• Verifying non-functional properties such as timing and power consumption by simulation
• A seamless tool chain for formal properties, connected to CIRCT and Yosys

The aim is a complete open-source verification chain that frees teaching and industry from expensive licences.

Our contribution

Together with TU Munich we work on the non-functional properties: tools that estimate the timing and power consumption of instruction set extensions. A first stocktaking is the systematic literature review IC Power Modeling in the Era of Machine Learning: Where Do We Stand? by Tavia Plattenteich, Philipp Fengler, Mladen Berekovic, Ulf Schlichtmann and Saleh Mulhem.

Partners and funding

Coordinated by Munich University of Applied Sciences (HM), with PlanV, TU Darmstadt, TU Munich and the University of Lübeck; further partners are TU Wien, MINRES Technologies and Yosys. Funded by the German Federal Ministry of Research, Technology and Space (then BMBF) under the DE:Sign call of the microelectronics design initiative.