Research staff

Dr.-Ing. Rolf Meyer

Research Group Leader

Portrait of Dr.-Ing. Rolf Meyer
Email
r.meyer@uni-luebeck.de
Phone
+49 451 3101 6336
Office
Building 64, Room 114 (2nd Floor)
Address
Universität zu Lübeck
Institut für technische Informatik
Ratzeburger Allee 160
23562 Lübeck
Germany

Research interests

Rolf Meyer works on designing embedded hardware and its software together, so that it is clear early on whether a system will meet its requirements for timing, energy and dependability. At the ITI he leads the research field Embedded System Design with the research groups Embedded Systems and HW/SW Co-Design.

  • Virtual platforms in SystemC/TLM: simulating systems before the chip or the FPGA bitstream exists
  • HW/SW co-design and design space exploration: finding the split between hardware and software with tools
  • Digital twins calibrated by measurement: real timing and energy profiles are fed back into the model
  • AI on embedded hardware: neural networks on RISC-V processors and microcontrollers
  • Security and dependability: side-channel analysis at register-transfer and netlist level, mixed criticality

Applications come from space, automotive, industrial automation and robotics.

Current projects

As principal investigator at the University of Lübeck, Rolf Meyer is currently responsible for three projects:

  • Shift2SDV (EU, Chips Joint Undertaking, 2025 to 2028): detecting attacks on over-the-air updates in the software-defined vehicle. A digital twin compares a new software version with the old one before it reaches the vehicle.
  • SSVEKI (ZIM, 2025 to 2026): embedded AI that detects collisions between vehicles and vulnerable road users in real time, together with consider it GmbH.
  • TwinSpace (BMWE, GreenTech, 2022 to 2026): load profiles from simulation, to make safety-relevant software for embedded systems use fewer resources.

Before that he worked in EMDrive, EEmotion, EMPHASE, Arrowhead Tools, EMC2 and SoCRocket, among others.

Career

  • since 2024: postdoc and leader of a research group at the Institute of Computer Engineering, University of Lübeck
  • 2024: Dr.-Ing. from TU Braunschweig (magna cum laude), supervised by Prof. Dr.-Ing. Mladen Berekovic. Thesis: Universal Scripting Interface: a universal scripting interface for SystemC, using SoCRocket as an example (in German)
  • 2018 to 2024: research associate at the Institute of Computer Engineering, University of Lübeck
  • 2012 to 2018: research associate at the Institute of Computer and Network Engineering, TU Braunschweig: SoCRocket for the European Space Agency (ESA), EU project EMC2
  • since 2012: managing director of embeddedfactor GmbH, a spin-off of TU Braunschweig, today also its technical lead: industrial projects in embedded systems, automotive and edge AI
  • 2010 to 2012: research associate at the Chair of Computer Architecture and Communication, Friedrich Schiller University Jena
  • 2010: Diplom (master's level) in Information Systems Engineering, TU Braunschweig, focus on HW/SW co-design and distributed systems
  • 2009: industrial placement in the mbed team at Arm, Cambridge, United Kingdom

Teaching

Summer semester

  • Real-Time Systems (CS4160, Master's), lecture and exercise, in English: foundations and applications of real-time systems, for Computer Science, Medical Informatics, IT Security and Robotics and Autonomous Systems, among others
  • Energy Efficiency in Embedded Systems (CS4720, Master's), lecture and exercise, in English: where power dissipation comes from and how to use the available hardware efficiently at system level
  • Embedded Systems (CS2101, Bachelor's), lecture and exercise, in German: foundations and applications of embedded systems for six Bachelor's programmes

Winter semester

  • Hardware/Software Co-Design (CS5170, Master's), lecture and exercise, in German: system modelling, synthesis, scheduling, binding and HW/SW partitioning, with SystemC as the description language
  • Tools for Scientific Work (CS2450, Bachelor's), seminar, in German: Python for machine learning and data science, LaTeX, Markdown, Jupyter and git

Theses

Rolf Meyer supervises Bachelor's and Master's theses on virtual platforms (SystemC/TLM, RISC-V), HW/SW co-design, AI on embedded hardware and digital twins. Since 2024 he has supervised nine Bachelor's and seven Master's theses. If you are interested, send a short email with your programme, your background and the topic that appeals to you.

Send an email

Research software

  • SoCRocket (GPL): a virtual platform in SystemC/TLM-2.0 for LEON3-based multicore systems, built for ESA, with Thomas Schuster
  • BuddelChip (MIT): a RISC-V platform in SystemC/TLM-2.0 for research and teaching, with Celine Thermann and Ahmed Mahmoudi
  • SCA-WAL (open source): assessing power side channels at register-transfer and netlist level, presented in IEEE Embedded Systems Letters 2025

Online

Research

Teaching

WiSe 2026/27

Earlier semesters (7)
SoSe 2026
Eingebettete Systeme, Energy Efficiency in Emebedded Systems (Energieeffizienz in eingebetteten Systemen), Real-Time Systems, Real-Time Systems for Master-AI
WiSe 2025/26
Hardware/Software Co-Design, Werkzeuge für das wissenschaftliche Arbeiten (Werkzeuge)
WiSe 2024/25
Hardware/Software Co-Design, Werkzeuge für das wissenschaftliche Arbeiten (Werkzeuge)
SoSe 2024
Energieeffizienz in eingebetteten Systemen
WiSe 2023/24
Hardware/Software Co-Design, Werkzeuge für das wissenschaftliche Arbeiten
SoSe 2022
Systemarchitekturen für Multimedia
WiSe 2021/22
Hardware/Software Co-Design

Projects

Completed projects

Publications

R. Meyer, B. Farkas, S. A. A. Shah, and M. Berekovic
Transparent SystemC Model Factory for Scripting Languages
Design and Verification Conference (DVCon) United States 2017, February 27 - March 2, 2017 , San Jose, CA USA, 2,017
RIS, BibTex
H. Isakovic, R. Grosu, D. Ratasich, J. Kadlec, Z. Pohl, S. Kerrison, K. Georgiou, K. Eder, et al.
A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC^2
Computer Safety, Reliability, and Security - SAFECOMP 2017 Workshops, ASSURE, DECSoS, SASSUR, TELERISE, and TIPS, Trento, Italy, September 12, 2017, Proceedings, 2,017
URL, DOI, RIS, BibTex
S. A. A. Shah, S. Horsinka, B. Farkas, R. Meyer, and M. Berekovic
Automatic Exploration of Hardware/Software Partitioning
Design and Verification Conference (DVCon) United States 2017, February 27 - March 2, 2017 , San Jose, CA USA, 2,017
RIS, BibTex
S. A. A. Shah, B. Farkas, R. Meyer, and M. Berekovic
Accelerating MPSoC Design Space Exploration Within System-Level Frameworks
The IEEE Nordic Circuits and Systems Conference (NORCAS), 1-2 November 2016 Copenhagen, Denmark, 2,016
RIS, BibTex
B. Farkas, S. A. A. Shah, J. Wagner, R. Meyer, R. Buchty, and M. Berekovic
An Open and Flexible SystemC to VHDL Workflow for Rapid Prototyping
Design and Verification Conference (DVCon) Europe 2016, October 19 - 20, 2016 Munich, Germany, 2,016
RIS, BibTex
P. Siegl, R. Buchty, B. Farkas, S. A. Horsinka, R. Meyer, J. Wagner, and M. Berekovic
The Past, Present and Future of the Open-Source Virtual Platform SoCRocket
Proceedings of the 2016 Workshop on Mixed Criticality Applications and Implementation Approaches, EMC^2@HiPEAC 2016, Prague, Czech Republic, January 20, 2016, 2,016
RIS, BibTex
R. Meyer, J. Wagner, R. Buchty, and M. Berekovic
Universal Scripting Interface for SystemC
DVCon Europe Conference Proceedings 2015, 2,015
URL, RIS, BibTex
J. Wagner, R. Meyer, R. Buchty, and M. Berekovic
A scriptable, standards-compliant reporting and logging extension for SystemC
Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on, 2,015
URL, DOI, RIS, BibTex
J. Wagner and R. Meyer
TLM Modeling for Space Applications
ACACES 2015 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems, HiPEAC, 2,015
RIS, BibTex
T. Schuster, R. Meyer, R. Buchty, L. Fossati, and M. Berekovic
SoCRocket - A virtual platform for the European Space Agency's SoC development
Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014 9th International Symposium on, 2,014
DOI, RIS, BibTex
S. A. Horsinka, R. Meyer, J. Wagner, R. Buchty, and M. Berekovic
On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design Exploration
NoCArc '14: Proceedings of the 2014 International Workshop on Network on Chip Architectures, ACM, 2,014, ISBN 978-1-4503-3064-0
DOI, ISBN, RIS, BibTex
L. Fossati, T. Schuster, R. Meyer, and M. Berekovic
SoCRocket: A virtual platform for SoC design
Proceedings of DASIA 2013 : DAta Systems In Aerospace : 14-16 May 2013, Porto, Portugal, 2,013
RIS, BibTex