Forschung
Im Rahmen eines DFG-Projektes wird an Hardwarebeschleunigung von Sematic Web Datenbanken durch dynamisch rekonfigurierbaren FPGAs geforscht.
Im Sematic Web werden Zusammenhänge durch sogenannte Tripel (Subjekt, Prädikat, Objekt) erzeugt. Die enorme Menge an Informationen benötigen geeignete Datenstrukturen, auf welche hoch parallelisiert und effizient zugegriffen werden kann. Im Zuge des Projektes soll sowohl die Erzeugung, als auch die Anfrageverarbeitung an einer solchen Datenbank durch Hardwarebeschleunigung erforscht werden.
Desweiteren entwickle ich eine echtzeitfähige Messplattform auf FPGA-basis für biophysikalische Anwendungen.
Abschlussarbeiten
Ich biete Arbeiten im Bereich digitalen Schaltungsentwurf für FPGAs an und andere FPGA basierte Anwendungen an. Für konkrete Themen sprechen Sie mich einfach persönlich an.
Lehre
Wintersemester
– Computergestützter Schaltungsentwurf (Übung/Praktikum)
Sommersemester
– Parallelrechnersysteme (Übung/Praktikum)
Lehre
Semesterunabhängig
WiSe 2026/27
Frühere Semester (15)
- SoSe 2026
- Rechnerarchitektur
- WiSe 2025/26
- Hardwarepraktikum, Parallelrechnersysteme
- WiSe 2024/25
- Chipdesign/Computergestützter Schaltungsentwurf, Hardware/Software Co-Design, Hardwarepraktikum, Parallel Computing Systems for Master-AI, Parallelrechnersysteme, Praktikum Systemarchitektur
- SoSe 2024
- Rechnerarchitektur, Systemarchitekturen für Multimedia
- WiSe 2023/24
- Chipdesign/Computergestützter Schaltungsentwurf, Hardware/Software Co-Design
- SoSe 2023
- Rechnerarchitektur
- SoSe 2022
- Rechnerarchitektur
- WiSe 2021/22
- Hardware/Software Co-Design
- SoSe 2021
- Eingebettete Systeme, Systemarchitekturen für Multimedia
- WiSe 2020/21
- Computergestützter Schaltungsentwurf, Hardware/Software Co-Design
- SoSe 2020
- Eingebettete Systeme
- WiSe 2019/20
- Hardware/Software Co-Design, Technische Grundlagen der Informatik 2
- SoSe 2019
- Eingebettete Systeme, Parallelrechnersysteme
- SoSe 2018
- Eingebettete Systeme, Parallelrechnersysteme
- WiSe 2016/17
- Hardware/Software Co-Design, Technische Grundlagen der Informatik 2
Projekte
Abgeschlossene Projekte
Publikationen
C. Blochwitz,
P. Grothe,
S. Dreier,
W. Aljnabi,
R. Buchty, and
M. Berekovic
RemEduLa - Remote Education Laboratory for FPGA Design Technology
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 1773-1777, IEEE, 2022, 2.022
URL, RIS, BibTex
RemEduLa - Remote Education Laboratory for FPGA Design Technology
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 1773-1777, IEEE, 2022, 2.022
URL, RIS, BibTex
A. Dörflinger,
M. Albers,
B. Kleinbeck,
Y. Guan,
H. Michalik,
R. Klink,
C. Blochwitz,
A. Nechi,
et al.
A comparative survey of open-source application-class RISC-V processor implementations
CF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers, ACM, 2021, 2.021
URL, DOI, RIS, BibTex
A comparative survey of open-source application-class RISC-V processor implementations
CF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers, ACM, 2021, 2.021
URL, DOI, RIS, BibTex
C. Blochwitz,
L. Philipp,
M. Berekovic, and
P. T.
StreamGrid - An AXI-Stream-Compliant Overlay Architecture
International Symposium on Applied Reconfigurable Computing, ARC 2021, 156-170, Springer, Cham, 2021, 2.021
URL, RIS, BibTex
StreamGrid - An AXI-Stream-Compliant Overlay Architecture
International Symposium on Applied Reconfigurable Computing, ARC 2021, 156-170, Springer, Cham, 2021, 2.021
URL, RIS, BibTex
D. Heinrich,
S. Werner,
C. Blochwitz,
T. Pionteck, and
S. Groppe
Hardware-aided update acceleration in a hybrid Semantic Web database system
The Journal of Supercomputing, 2020, 2.020
RIS, BibTex
Hardware-aided update acceleration in a hybrid Semantic Web database system
The Journal of Supercomputing, 2020, 2.020
RIS, BibTex
C. Blochwitz,
J. Wolff,
M. Berekovic,
D. Heinrich,
S. Groppe,
J. Joseph, and
P. T.
Hardware-Triplestore – a Hardware-centric Database for Semantic Web
International Conference on Field-Programmable Technology, 2018, 2.018
RIS, BibTex
Hardware-Triplestore – a Hardware-centric Database for Semantic Web
International Conference on Field-Programmable Technology, 2018, 2.018
RIS, BibTex
J. M. Joseph,
M. Mey,
K. Ehlers,
C. Blochwitz,
T. Winker, and
T. Pionteck
Design Space Exploration for a Hardware-accelerated Embedded Real-Time Pose Estimation using Vivado HLS
ReConFig 2017, 2017, 2.017
RIS, BibTex
Design Space Exploration for a Hardware-accelerated Embedded Real-Time Pose Estimation using Vivado HLS
ReConFig 2017, 2017, 2.017
RIS, BibTex
J. Joseph,
C. Blochwitz,
A. García-Ortiz, and
T. Pionteck
Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs
MICPRO 2460, 36–47, Elsevier, Amsterdam 2017, 2.017
URL, RIS, BibTex
Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs
MICPRO 2460, 36–47, Elsevier, Amsterdam 2017, 2.017
URL, RIS, BibTex
C. Blochwitz,
J. Wolff,
J. M. Joseph,
S. Werner,
D. Heinrich,
S. Groppe, and
T. Pionteck
Hardware-accelerated Radix-Tree based string sorting for Big Data applications
30TH INTERNATIONAL CONFERENCE ON ARCHITECTURE OF COMPUTING SYSTEMS, Wien, 47-58, Springer, Cham 2017, 2.017
URL, RIS, BibTex
Hardware-accelerated Radix-Tree based string sorting for Big Data applications
30TH INTERNATIONAL CONFERENCE ON ARCHITECTURE OF COMPUTING SYSTEMS, Wien, 47-58, Springer, Cham 2017, 2.017
URL, RIS, BibTex
C. Blochwitz,
R. Klink,
J. M. Joseph, and
T. Pionteck
Contentious Live-Tracing as Debugging Approach on FPGAs
To Appear: ReConFig 2017, IEEE, Cancun, Mexiko 2017, 2.017
RIS, BibTex
Contentious Live-Tracing as Debugging Approach on FPGAs
To Appear: ReConFig 2017, IEEE, Cancun, Mexiko 2017, 2.017
RIS, BibTex
S. Werner,
D. Heinrich,
S. Groppe,
C. Blochwitz, and
T. Pionteck
Runtime Adaptive Hybrid Query Engine based on FPGAs
Open Journal of Databases (OJDB), 2016, 2.016
URL, RIS, BibTex
Runtime Adaptive Hybrid Query Engine based on FPGAs
Open Journal of Databases (OJDB), 2016, 2.016
URL, RIS, BibTex
J. M. Joseph,
T. Winker,
K. Ehlers,
C. Blochwitz, and
T. Pionteck
Hardware-Accelerated Pose Estimation for Embedded Systems using Vivado HLS
ReConFig, Cancun, Mexiko 2016, 2.016
URL, DOI, RIS, BibTex
Hardware-Accelerated Pose Estimation for Embedded Systems using Vivado HLS
ReConFig, Cancun, Mexiko 2016, 2.016
URL, DOI, RIS, BibTex
J. M. Joseph,
S. Wrieden,
C. Blochwitz,
A. García-Ortiz, and
T. Pionteck
A Simulation Environment for Design Space Exploration for Asymmetric 3D-Network-on-Chip
11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), Tallinn 2016, 2.016
URL, DOI, RIS, BibTex
A Simulation Environment for Design Space Exploration for Asymmetric 3D-Network-on-Chip
11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), Tallinn 2016, 2.016
URL, DOI, RIS, BibTex
J. Joseph,
C. Blochwitz, and
T. Pionteck
Adaptive Allocation of Default Router Paths in Network-on-Chips for Latency Reduction
2016 International Conference on High Performance Computing & Simulation (HPCS), Innsbruck 2016, 2.016
URL, RIS, BibTex
Adaptive Allocation of Default Router Paths in Network-on-Chips for Latency Reduction
2016 International Conference on High Performance Computing & Simulation (HPCS), Innsbruck 2016, 2.016
URL, RIS, BibTex
S. Groppe,
D. Heinrich,
C. Blochwitz, and
T. Pionteck
Constructing Large-Scale Semantic Web Indices for the Six RDF Collation Orders
Open Journal of Big Data (OJBD), 2016, 2.016
URL, RIS, BibTex
Constructing Large-Scale Semantic Web Indices for the Six RDF Collation Orders
Open Journal of Big Data (OJBD), 2016, 2.016
URL, RIS, BibTex
S. Werner,
D. Heinrich,
J. Piper,
S. Groppe,
R. Backasch,
C. Blochwitz, and
T. Pionteck
Automated Composition and Execution of Hardware-accelerated Operator Graphs
To Appear: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), IEEE, Bremen 2015, 2.015
RIS, BibTex
Automated Composition and Execution of Hardware-accelerated Operator Graphs
To Appear: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), IEEE, Bremen 2015, 2.015
RIS, BibTex
D. Heinrich,
S. Werner,
M. Stelzner,
C. Blochwitz,
T. Pionteck, and
S. Groppe
Hybrid FPGA Approach for a B+ Tree in a Semantic Web Database System
To Appear: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), IEEE, Bremen 2015, 2.015
RIS, BibTex
Hybrid FPGA Approach for a B+ Tree in a Semantic Web Database System
To Appear: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), IEEE, Bremen 2015, 2.015
RIS, BibTex
S. Groppe,
D. Heinrich,
S. Werner,
C. Blochwitz, and
T. Pionteck
PatTrieSort - External String Sorting based on Patricia Tries
Open Journal of Databases (OJDB), 2015, 2.015
URL, RIS, BibTex
PatTrieSort - External String Sorting based on Patricia Tries
Open Journal of Databases (OJDB), 2015, 2.015
URL, RIS, BibTex
C. Blochwitz,
J. M. Joseph,
T. Pionteck,
R. Backasch,
S. Werner,
D. Heinrich, and
S. Groppen
An optimized Radix-Tree for hardware-accelerated index generation for Semantic Web Databases
To Appear: International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexiko 2015, 2.015
RIS, BibTex
An optimized Radix-Tree for hardware-accelerated index generation for Semantic Web Databases
To Appear: International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexiko 2015, 2.015
RIS, BibTex