Mitarbeiter

Prof. Dr.-Ing. Mladen Berekovic

Institutsdirektor


Ratzeburger Allee 160
23562 Lübeck
Gebäude 64, Raum 118 (2.OG)

Email:berekovic(at)iti.uni-luebeck.de
Telefon:+49 451 3101 6300
Fax:+49 451 3101 6304

Publikationen

[JuB19] Jungklass, P.; Berekovic, M. : MemOpt: Automated Memory Distribution for Multicore Microcontrollers with Hard Real-Time Requirements. 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), IEEE, Helsinki, Finland 2019 [Abstract]
[JuB19a] Jungklass, P.; Berekovic, M.: Cache-Kohärenz für embedded Multicore-Mikrocontroller mit harter Echtzeitanforderung. Echtzeit 2019, 129-138, Springer Vieweg, Wiesbaden 2019 [Paper]
[BWB18] Blochwitz, C.; Wolff, J.; Berekovic, M.;Heinrich, D.; Groppe, S.; Joseph, JM.; Pionteck T.: Hardware-Triplestore – a Hardware-centric Database for Semantic Web. International Conference on Field-Programmable Technology, 2018
[MFS17] Meyer, R.;Farkas, B.; S. A. A. Shah; Berekovic, M.:: Transparent SystemC Model Factory for Scripting Languages. Design and Verification Conference (DVCon) United States 2017, San Jose, CA USA 2017
[MMD17] L. Mattii, D. M. Milojevic, P. Debacker, Y. Sherazi, M. Berekovic, and P. Raghavan: IR-drop aware Design technology co-optimization for N5 node with different device and cell height options. 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017
[SBB17] P. Siegl, R. Buchty, and M. Berekovic: A Bandwidth Accurate, Flexible and Rapid Simulating Multi-HMC Modelling Tool. Proceedings of the Third International Symposium on Memory Systems, MEMSYS 2017, ACM, Washington, DC, USA 2017
[SHF17] S. A. A. Shah, S. Horsinka, B. Farkas, R. Meyer, and M. Berekovic: Automatic Exploration of Hardware/Software Partitioning. Design and Verification Conference (DVCon) United States 2017, San Jose, CA USA 2017
[BMH16] P. Bahmanyar, M. Maymandi-Nejad, S. Hosseini-Khayat, and M. Berekovic: Design and Analysis of an Ultra-low-power Double-tail Latched Comparator for Biomedical Applications. Analog Integrated Circuits and Signal Processing, 86(2), 2016
[FSW16] B. Farkas, S. A. A. Shah, J. Wagner, R. Meyer, R. Buchty, and M. Berekovic: An Open and Flexible SystemC to VHDL Workflow for Rapid Prototyping. Design and Verification Conference (DVCon) Europe 2016, Munich, Germany, 2016
[MWF16] R. Meyer, J. Wagner, B. Farkas, S. Horsinka, P. Siegl, R. Buchty, and M. Berekovic: A Scriptable Standard-Compliant Reporting and Logging Framework for SystemC. ACM Trans. Embed. Comput. Syst., 16(1), ACM, 2016
[SBB16] P. Siegl, R. Buchty, and M. Berekovic: Data-Centric Computing Frontiers: A Survey On Processing-In-Memory. Proceedings of the Second International Symposium on Memory Systems, MEMSYS 2016, ACM, Washington, DC, USA 2016
[SBB16a] P. Siegl, R. Buchty, and M. Berekovic: Towards Bridging the Gap Between Academic and Industrial Heterogeneous System Architecture Design Space Exploration. Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation - Methods and Tools, RAPIDO@HiPEAC 2016, ACM, Prague, Czech Republic 2016
[SBF16] P. Siegl, R. Buchty, B. Farkas, S. A. Horsinka, R. Meyer, J. Wagner, and M. Berekovic: The Past, Present and Future of the Open-Source Virtual Platform SoCRocket. Proceedings of the 2016 Workshop on Mixed Criticality Applications and Implementation Approaches, EMC^2@HiPEAC 2016, Prague, Czech Republic 2016
[SFM16] S. A. A. Shah, B. Farkas, R. Meyer, and M. Berekovic: Accelerating MPSoC Design Space Exploration Within System-Level Frameworks. The IEEE Nordic Circuits and Systems Conference (NORCAS), Copenhagen, Denmark 2016
[MMS15] S. Michalik, R. Meyer, P. Siegl, M. Berekovic, and L. Fossati: TLM Design Space Exploration for a Hardware CFDP Transmission Accelerator. SEA-Publications, 2015
[MWB15] R. Meyer, J. Wagner, R. Buchty, and M. Berekovic: Universal Scripting Interface for SystemC. DVCon Europe Conference Proceedings 2015, 2015
[QiB15] S. Qin and M. Berekovic: A Comparison of High-Level Design Tools for SoC-FPGA on Disparity Map Calculation Example. CoRR, 150900036, 2015
[SBB15] P. Siegl, R. Buchty, and M. Berekovic: Revealing Potential Performance Improvements By Utilizing Hybrid Work-Sharing For Resource-Intensive Seismic Applications. Proceedings of the 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015, IEEE Computer Society, Turku, Finland 2015
[WMB15] J. Wagner, R. Meyer, R. Buchty, and M. Berekovic: A scriptable, standards-compliant reporting and logging extension for SystemC. Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on, 2015
[ABM14] H. Al-Khalissi, M. Berekovic, and A. Marongiu: On the Relevance of Architectural Awareness for Efficient Fork/Join Support on Cluster-Based Manycores. MES14: Proceedings of International Workshop on Manycore Embedded Systems, ACM, 2014
[ASB14] H. Al-Khalissi, S. A. A. Shah, and M. Berekovic: An Efficient Barrier Implementation for OpenMP-Like Parallelism on the Intel SCC. PDP14: Proceedings of the 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, IEEE Computer Society, 2014
[FSB14] B. Farkas, H. Schrom, and M. Berekovic: BEM: Der Building-Energy-Manager fuer das Smart-Home der Zukunft. VDE Kongress 2014, 2014
[HMW14] S. A. Horsinka, R. Meyer, J. Wagner, R. Buchty, and M. Berekovic: On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design Exploration. NoCArc14: Proceedings of the 2014 International Workshop on Network on Chip Architectures, ACM, 2014
[SMB14] T. Schuster, R. Meyer, R. Buchty, L. Fossati, and M. Berekovic: SoCRocket - A virtual platform for the European Space Agency`s SoC development. Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014 9th International Symposium on, 2014
[SWS14] S. A. A. Shah, J. Wagner, T. Schuster, and M. Berekovic: A lightweight-system-level power and area estimation methodology for application specific instruction set processors. Power and Timing Modeling, Optimization and Simulation (PATMOS), 2014 24th International Workshop on, 2014
[TRG14] I. Tsekoura, G. Rebel, P. Glosekotter, and M. Berekovic: An evaluation of energy efficient microcontrollers. Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014 9th International Symposium on, 2014
[ABB13] H. Al-Khalissi, R. Buchty, and M. Berekovic: Efficient Barrier Synchronization for OpenMP-Like Parallelism on the Intel SCC. ICPADS `13: Proceedings of the 2013 International Conference on Parallel and Distributed Systems, IEEE Computer Society, 2013
[AMB13] H. Al-Khalissi, A. Marongiu, and M. Berekovic: An approach for Supporting OpenMP on the Intel SCC. SPLASH-MARC, 2013
[FSM13] L. Fossati, T. Schuster, R. Meyer, and M. Berekovic: SoCRocket: A virtual platform for SoC design. Proceedings of DASIA 2013 : DAta Systems In Aerospace : 14-16 May 2013, Porto, Portugal 2013
[MDA13] B. Motruk, J. Diemer, P. Axer, R. Buchty, and M. Berekovic: Safe Virtual Interrupts Leveraging Distributed Shared Resources and Core-to-Core Communication on Many-Core Platforms. PRDC `13: Proceedings of the 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing, IEEE Computer Society, 2013
[MDB13] B. Motruk, J. Diemer, R. Buchty, and M. Berekovic: Power monitoring for mixed-criticality on a many-core platform. ARCS`13: Proceedings of the 26th international conference on Architecture of Computing Systems, Springer-Verlag, 2013
[WBS13] J. Wagner, R. Buchty, C. Schubert, and M. Berekovic: Designing a low-power wireless sensor node rASIP architecture. Signal Processing Systems (SiPS), 2013 IEEE Workshop on, 2013
[AMB12] H. Al-Khalissi, A. Marongiu, and M. Berekovic: Low-Overhead Barrier Synchronization for OpenMP-like Parallelism on the Single-Chip Cloud Computer. Many-core Applications Research Community (MARC) Symposium at RWTH Aachen University, 2012
[BCE12] M. Berekovic, S. Chakraborty, P. Eles, and A. D. Pimentel: Introduction to the Special Section on ESTIMedia’08. ACM Transactions in Embedded Computing Systems, ACM, 2012
[MDB12] B. Motruk, J. Diemer, R. Buchty, R. Ernst, and M. Berekovic: IDAMC: A Many-Core Platform with Run-Time Monitoring for Mixed-Criticality. HASE `12: Proceedings of the 2012 IEEE 14th International Symposium on High-Assurance Systems Engineering, IEEE Computer Society, 2012
[AlB11] H. Al-Khalissi and M. Berekovic: Performance of RCCE Broadcast Algorithm in SCC. MARC Symposium, 2011
[BBB10] D. Bode, M. Berekovic, A. Borkowski, and L. Buker: QoR Analysis of Automated Clock-Mesh Implementation under OCV Consideration. Euromicro Symposium on Digital Systems Design, 2010
[BeP10] M. Berekovic and A. D. Pimentel: Editorial. J. Signal Process. Syst., 60(2), 2010
[HBH10] M. Hartmann, T. V. Aa, M. Berekovic, and C. Hochberger: Still Image Processing on Coarse-Grained Reconfigurable Array Architectures. Journal of Signal Processing Systems, 60, 2010
[KrB10] T. Kranich and M. Berekovic: NoC Switch with Credit Based Guaranteed Service Support Qualified for GALS Systems. DSD `10: Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, IEEE Computer Society, 2010
[NSB10] J. Naghmouchi, D. P. Scarpazza, and M. Berekovic: Small-ruleset regular expression matching on GPGPUs: quantitative performance analysis and optimization. ICS `10: Proceedings of the 24th ACM International Conference on Supercomputing, ACM, 2010
[BCD09] M. Berekovic, V. Chaudhary, A. Dean, and J. Fritts: Editorial. Microprocess. Microsyst., 33(4), 2009
[BGH09] C. Bachmann, A. Genser, J. Hulzink, M. Berekovic, and C. Steger: A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing. DATE `09: Proceedings of the Conference on Design, Automation and Test in Europe, European Design and Automation Association, 2009
[BHS09] M. Berekovic, M. Hanke, T. Schuster, T. Kranich, and R. Ernst: ESL design in the context of embedded systems education. WESE `09: Proceedings of the 2009 Workshop on Embedded Systems Education, ACM, 2009
[BKM09] M. Berekovic, A. Kanstein, B. Mei, and B. D. Sutter: Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor. Microprocessors and Microsystems, 33, 2009
[GBS09] A. Genser, C. Bachmann, C. Steger, J. Hulzink, and M. Berekovic: Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing. ASAP `09: Proceedings of the 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, IEEE Computer Society, 2009
[YNH09] L. Yseboodt, M. D. Nil, J. Huisken, M. Berekovic, Q. Zhao, F. Bouwens, J. Hulzink, and J. V. Meerbergen: Design of 100 μW Wireless Sensor Nodes for Biomedical Monitoring. Journal of Signal Processing Systems, 57, 2009
[BBA08] M. Berekovic, F. Bouwens, T. V. Aa, and D. Verkest: Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor. Workshop on Power and Timing Modeling, Optimization and Simulation, 2008
[BBS08] F. Bouwens, M. Berekovic, B. D. Sutter, and G. Gaydadjiev: Architecture enhancements for the ADRES coarse-grained reconfigurable array. HiPEAC`08: Proceedings of the 3rd international conference on High performance embedded architectures and compilers, Springer-Verlag, 2008
[BBS08a] F. Bouwens, M. Berekovic, B. D. Sutter, and G. Gaydadjiev: Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array. High Performance Embedded Architectures and Compilers, 2008
[BDW08] M. Berekovic, N. J. Dimopoulos, and S. Wong: Embedded Computer Systems: Architectures, Modeling, and Simulation, 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008. Proceedings. Systems, Architectures, Modeling, and Simulation, 2008
[BeN08] M. Berekovic and T. Niggemeier : A distributed, simultaneously multi-threaded (SMT) processor with clustered scheduling windows for scalable DSP performance. J. Signal Process. Syst., 50(2), 2008
[BeN08a] M. Berekovic and T. Niggemeier: A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance. Journal of Signal Processing Systems, 50, 2008
[BHK08] M. Berekovic, C. Hochberger, and A. Koch: Rekonfigurierbare Architekturen. Informatik Spektrum, 31, 2008
[BPH08] M. Berekovic, A. D. Pimentel, and T. D. Hämäläinen: Editorial. J. Syst. Archit., 54(11), 2008
[GBA08] A. Garcia, M. Berekovic, and T. V. Aa: Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor. ASAP `08: Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors, IEEE Computer Society, 2008
[GHB08] J. Govers, J. Huisken, M. Berekovic, O. Rousseaux, F. Bouwens, M. de Nil, and J. V. Meerbergen: Implementation of an UWB impulse-radio acquisition and despreading algorithm on a low power ASIP. HiPEAC`08: Proceedings of the 3rd international conference on High performance embedded architectures and compilers, Springer-Verlag, 2008
[GHB08a] J. Govers, J. Huisken, M. Berekovic, O. Rousseaux, F. Bouwens, M. D. Nil, and J. L. V. Meerbergen: Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP. High Performance Embedded Architectures and Compilers, 2008
[PGB08] F. Pratas, G. Gaydadjiev, M. Berekovic, L. Sousa, and S. Kaxiras: Low power microarchitecture with instruction reuse. CF `08: Proceedings of the 5th conference on Computing frontiers, ACM, 2008
[PGV08] J. Penders, B. Gyselinckx, R. Vullers, O. Rousseaux, M. Berekovic, M. D. Nil, C. V. Hoof, J. Ryckaert, et al.: Human++: Emerging Technology for Body Area Networks. , 2008
[WKM08] K. Wu, A. Kanstein, J. Madsen, and M. Berekovic: MT-ADRES: multi-threading on coarse-grained reconfigurable architecture. International Journal of Electronics, 95, 2008
[AKL07] C. Arbelo, A. Kanstein, S. Lopez, J. Lopez, M. Berekovic, R. Sarmiento, and J.-Y. Mignolet: Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: the H.264/AVC Deblocking Filter. Design, Automation Test in Europe Conference Exhibition, 2007. DATE `07, 2007
[BBK07] F. Bouwens, M. Berekovic, A. Kanstein, and G. Gaydadjiev: Architectural exploration of the ADRES coarse-grained reconfigurable array. ARC`07: Proceedings of the 3rd international conference on Reconfigurable computing, Springer-Verlag, 2007
[BBK07a] F. Bouwens, M. Berekovic, A. Kanstein, and G. Gaydadjiev: Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array. Applied Reconfigurable Computing, 2007
[Ber07] M. Berekovic: Ulta-Low-Power Wireless Sensor Node Design on 100 uW Scavenging Energy for Applications In Biomedical Monitoring. DSD `07: Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, IEEE Computer Society, 2007
[HAB07] M. Hartmann, T. V. Aa, M. Berekovic, C. Hochberger, and B. D. Sutter: Still Image Processing on Coarse-Grained Reconfigurable Array Architectures. Embedded Systems for Real-Time Multimedia, 2007
[JEK07] J. W. M. Jacobs, L. V. Engelen, J. Kuper, G. J. M. Smit, S. Vassiliadis, M. Berekovic, and T. D. Hamalainen: Image Quantisation on a Massively Parallel Embedded Processor. Systems, Architectures, Modeling, and Simulation, 2007
[LKL07] S. López, A. Kanstein, J. F. López, M. Berekovic, R. Sarmiento, and J.-Y. Mignolet: Toward the implementation of a baseline H.264/AVC decoder onto a reconfigurable architecture. , 2007
[NYB07] M. D. Nil, L. Yseboodt, F. Bouwens, J. Hulzink, M. Berekovic, J. Huisken, and J. van Meerbergen: Ultra Low Power ASIP Design for Wireless Sensor Nodes. , 2007
[VBH07] S. Vassiliadis, M. Berekovic, and T. D. Hämäläinen: Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings. Systems, Architectures, Modeling, and Simulation, 2007
[WKM07] K. Wu, A. Kanstein, J. Madsen, and M. Berekovic: MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture. Applied Reconfigurable Computing, 2007
[YNB07] L. Yseboodt, M. D. Nil, and M. Berekovic: Electrocardiogram on Wireless Sensor Nodes. Dagstuhl Seminars, 2007
[YNH07] L. Yseboodt, M. D. Nil, J. Huisken, M. Berekovic, Q. Zhao, F. Bouwens, and J. V. Meerbergen: Design of 100 μW wireless sensor nodes on energy scavengers for biomedical monitoring. SAMOS`07: Proceedings of the 7th international conference on Embedded computer systems, Springer-Verlag, 2007
[YNH07a] L. Yseboodt, M. D. Nil, J. Huisken, M. Berekovic, Q. Zhao, F. Bouwens, and J. L. V. Meerbergen: Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring. Systems, Architectures, Modeling, and Simulation, 2007
[BeN06] M. Berekovic and T. Niggemeier: A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme. Systems, Architectures, Modeling, and Simulation, 2006
[BeN06a] M. Berekovic and T. Niggemeier: A scalable, multi-thread, multi-issue array processor architecture for DSP applications based on extended tomasulo scheme. SAMOS`06: Proceedings of the 6th international conference on Embedded Computer Systems, Springer-Verlag, 2006
[BKM06] M. Berekovic, A. Kanstein, and B. Mei: Mapping MPEG Video Decoders on the ADRES Reconfigurable Array Processor for Next Generation MultiMode Mobile Terminals. , 2006
[SMB06] B. D. Sutter, B. Mei, A. Bartic, T. V. Aa, M. Berekovic, J.-y. Mignolet, K. Croes, P. Coene, et al.: Hardware and a Tool Chain for ADRES. Applied Reconfigurable Computing, 2006
[SBM05] H.-J. Stolberg, M. Berekovic, S. Moch, L. Friebe, M. B. Kulaczewski, S. Flügel, H. Klußmann, A. Dehnhardt, et al.: HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing. Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 41, 2005
[SBP05] H.-J. Stolberg, M. Berekovic, and P. Pirsch: A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications. Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 41, 2005
[BMP04] M. Berekovic, S. Moch, and P. Pirsch: A scalable, clustered SMT processor for digital signal processing. ACM Sigarch Computer Architecture News, 32, 2004
[SMF04] H.-J. Stolberg, S. Moch, L. Friebe, A. Dehnhardt, M. B. Kulaczewski, M. Berekovic, and P. Pirsch: An SoC with two multimedia DSPs and a RISC core for video compression applications. Solid-State Circuits IEEE International Conference, 2004
[BMP03] M. Berekovic, S. Moch, and P. Pirsch: A scalable, clustered SMT processor for digital signal processing. MEDEA `03: Proceedings of the 2003 workshop on MEmory performance, ACM, 2003
[FSB03] L. Friebe, H.-J. Stolberg, M. Berekovic, S. Moch, M. B. Kulaczewski, A. Dehnhardt, and R. Pirsch: HiBRID-SoC: a system-on-chip architecture with two multimedia DSPs and a RISC core. IEEE International System-on-Chip (SoC) Conference, 2003
[MBS03] S. Moch, M. Berekovic, H. J. Stolberg, L. Friebe, M. B. Kulaczewski, A. Dehnhardt, and P. Pirsch: HIBRID-SOC: a multi-core architecture for image and video applications. MEDEA `03: Proceedings of the 2003 workshop on MEmory performance, ACM, 2003
[PBS03] P. Pirsch, M. Berekovic, H.-J. Stolberg, and J. Jachalsky: VLSI architectures for MPEG. International Symposium on VLSI Technology, Systems and ApplicationsInternational Symposium on VLSI Technology, Systems and Applications, 2003
[SBF03] H.-J. Stolberg, M. Berekovic, L. Friebe, S. Moch, S. Flugel, X. Mao, M. B. Kulaczewski, H. Klusmann, et al.: HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications. DATE `03: Proceedings of the conference on Design, Automation and Test in Europe, IEEE Computer Society, 2003
[SBF03a] H.-J. Stolberg, M. Berekovic, L. Friebe, S. Moch, M. B. Kulaczewski, A. Dehnhardt, and P. Pirsch: HiBRID-SoC: a multi-core SoC architecture for multimedia signal processing. IEEE Workshop on Signal Processing Systems, 2003
[SBF03b] H.-J. Stolberg, M. Berekovic, L. Friebe, S. Moch, M. B. Kulaczewski, and P. Pirsch : HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing. Very Large Scale Integration, 2003
[SBF03c] H.-J. Stolberg, M. Berekovic, L. Friebe, S. Moch, S. Flügel, M. B. Kulaczewski, and P. Pirsch: HiBRID-SoC: a multi-core architecture for image and video applications. International Conference on Image Processing, 2003
[BPS02] M. Berekovic, P. Pirsch, T. Selinger, K.-i. Wels, C. Miro, A. Lafage, C. Heer, and G. Ghigo: Architecture of an Image Rendering CoProcessor for MPEG4 Visual Compositing. Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 31, 2002
[BSP02] M. Berekovic, H.-J. Stolberg, and P. Pirsch: Multicore system-on-chip architecture for MPEG4 streaming video. IEEE Transactions on Circuits and Systems for Video Technology, 12, 2002
[SBP02] H.-J. Stolberg, M. Berekovic, and P. Pirsch: A platform-independent methodology for performance estimation of streaming media applications. International Conference on Multimedia Computing and Systems/International Conference on Multimedia and Expo, 2002
[BSP01] M. Berekovic, H.-J. Stolberg, P. Pirsch, and H. Runge: A programmable co-porcessor for MPEG-4 video. ICASSP `01: Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference, IEEE Computer Society, 2001
[SBP01] H.-J. Stolberg, M. Berekovic, P. Pirsch, and H. Runge: The MPEG4 Advanced Simple profile - a complexity study. Workshop and Exhibition on Moving Picture Experts Group, 2001
[SBP01a] H.-J. Stolberg, M. Berekovic, P. Pirsch, and H. Runge: Implementing The MPEG4 Advanced Simple Profile For Streaming Video Applications. International Conference on Multimedia Computing and Systems/International Conference on Multimedia and Expo, 2001
[SBP01b] H. J. Stolberg, M. Berekovic, P. Pirsch, and H. Runge: The MPEG4 ad-vanced simple profile-a complexity study. , 2001
[BPS00] M. Berekovic, P. Pirsch, T. Selinger, K. -.-.. Wels, C. Miro, A. Lafage, C. Heer, and G. Ghigo: Architecture of an Image Rendering Co-Processor for MPEG-4 Systems. ASAP `00: Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, IEEE Computer Society, 2000
[BPS00a] M. Berekovic, P. Pirsch, T. Selinger, K.-I. Wels, C. Miro, A. Lafage, C. Heer, and G. Ghigo : Coprocessor architecture for MPEG4 main profile visual compositing. IEEE International Symposium on Circuits and Systems, 2000
[HML00] C. Heer, C. Miro, A. Lafage, M. Berekovic, G. Ghigo, T. Selinger, and K.-I. Wels: Coprocessor architecture for MPEG4 video object rendering. Visual Communications and Image Processing, 2000
[SBP00] H.-J. Stolberg, M. Berekovic, P. Pirsch, H. Runge, H. Moller, and J. Kneip: The M-PIRE MPEG4 codec DSP and its macroblock engine. IEEE International Symposium on Circuits and Systems, 2000
[BJP99] M. Berekovic, K. Jacob, and P. Pirsch: Architecture of a hardware module for MPEG4 shape decoding. IEEE International Symposium on Circuits and Systems, 1999
[BKM99] S. Bauer, J. Kneip, T. Mlasko, B. Schmale, J. Vollmer, A. Hutter, and M. Berekovic: The MPEG4 Multimedia Coding Standard: Algorithms, Architectures and Applications. Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 23, 1999
[BKP99] M. Berekovic, H. Kloos, and P. Pirsch: Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications. Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 22, 1999
[BSK99] M. Berekovic, H.-j. Stolberg, M. B. Kulaczewski, P. Pirsch, H. Möller, H. Runge, J. Kneip, and B. Stabernack: Instruction Set Extensions for MPEG4 Video. Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 23, 1999
[BSM99] M. Berekovic, T. Selinger, C. Miro, G. Ghigo, C. Heer, P. Pirsch, K.-I. Wels, and A. Lafage: The TANGRAM co-processor for MPEG4 visual compositing. IEEE Workshop on Signal Processing Systems, 1999
[HML99] C. Heer, C. Miro, A. Lafage, M. Berekovic, G. Ghigo, T. Selinger, and K. I. Wels: Design and architecture of the MPEG4 video rendering co-processor `TANGRAM`. Sealing Technology, 1999
[KBP99] H. Kloos, M. Berekovic, and P. Pirsch: Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-Anwendungen. Architektur von Rechensystemen, Systemarchitektur auf dem Weg ins 3. Jahrtausend: Neue Strukturen, Konzepte, Verfahren und Bewertungsmethoden - Vorträge der 15. GI/ITG-Fachtagung ARCS `99 und der APS`99 (Arbeitsplatzrechensysteme), VDE-Verlag GmbH, 1999
[BeP98] M. Berekovic and P. Pirsch: An Array Processor Architecture with Parallel Data Cache for Image Rendering and Compositing. CGI `98: Proceedings of the Computer Graphics International 1998, IEEE Computer Society, 1998
[BeP98a] M. Berekovic and P. Pirsch: Architecture of a coprocessor module for image compositing. Physica Medica, 1998
[BFP98] M. Berekovic, R. Frase, and P. Pirsch: A flexible processor architecture for MPEG4 image compositing. International Conference on Acoustics, Speech, and Signal Processing, 1998
[BHP98] M. Berekovic, D. Heistermann, and P. Pirsch: A core generator for fully synthesizable and highly parameterizable RISC-cores for system-on-chip designs. IEEE Workshop on Signal Processing Systems, 1998
[BMG98] M. Berekovic, G. Meyer, Y. Guo, and P. Pirsch: Multimedia RISC core for efficient bitstream parsing and VLD. , 1998
[BPK98] M. Berekovic, P. Pirsch, and J. Kneip: An Algorithm-Hardware-System Approach to VLIW Multimedia Processors. Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 20, 1998
[WHK98] J. P. Wittenburg, W. Hinrichs, J. Kneip, M. Ohmacht, M. Berekovic, H. Lieske, H. Kloos, and P. Pirsch: Realization of a programmable parallel DSP for high performance image processing applications. DAC `98: Proceedings of the 35th annual Design Automation Conference, 1998
[BKP97] M. Berekovic, H. Kloos, and P. Pirsch: Hardware realization of a Java virtual machine for high performance multimedia applications. IEEE Workshop on Signal Processing Systems, 1997
[KBP97] J. Kneip, M. Berekovic, and P. Pirsch: An algorithm-hardware-system approach to VLIW multimedia processors. Multimedia Signal Processing, 1997
[KBW97] J. Kneip, M. Berekovic, J. P. Wittenburg, W. Hinrichs, and P. Pirsch: An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor. Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology, 16, 1997
[PFB97] P. Pirsch, A. Freimann, and M. Berekovic: Architectural approaches for multimedia processors. , 1997
[KWB95] J. Kneip, J. P. Wittenburg, M. Berekovic, K. Ronner, and P. Pirsch: An algorithm adapted autonomous controlling concept for a parallel single-chip digital signal processor. Workshop on VLSI Signal Processing, 1995