ITI is a Lead Institution for Digital Implementation, Synthesis and Low-Power Verification in the Cadence Academic Network.

For a complete list of all network members please check out the official Cadence Academic Network Website.


We are relying on Cadence Tools in following classes:

  • Computer-aided Circuit Design (Computergestützter Schaltungsentwurf ) targets digital integrated circuits design with focus on full-system design. Starting with a detailed introduction into hardware definition languages and modelling of components, the lecture subsequently conveys theoretical and hands-on knowledge on full-system and SoC modeling.

    The corresponding Lab Course aims for the understanding of modern SoC design flow. Students implement an entire system in VHDL, comprising CPU, according I/O interfaces, and the attachment of physical devices to the prototype platform. Accordingly, they develop appropriate testbenches and synthesize the design down to place & route. In the course of the lab students learn how to use Cadence RTL Compiler, Incisive Unified Simulator and SoC Encounter. (link to lecture)

  • Hardware/Software Codesign teaches methods and algorithms for the joint development of a system’s hardware and software components. It hence focuses on general target architectures and the individual design steps, familiarizing the students with several approaches towards system modelling. Expanding the RTL knowledge conveyed by the lecture and lab course Computer-aided Circuit Design, particular focus is put on high-level system modeling.

    The correspoding Lab Course hence is dedicated to state-of-the-art modeling using SystemC and TLM2.0. The students gain hands-on knowledge with regard to system design, partitioning, and evaluating design quality. The lab heavily relies on the Cadence Incisive Unified Simulator for RTL / SystemC co-simulation (link to lab).

  • The above lectures build upon the foundation laid by the introductory lectures Technical Foundations of Computer Science (Technische Informatik) I/II, where students were introduced to logic gates, their technical realization (PMOS, NMOS, and CMOS essentials) and combination into higher functions such as adders, multiplexers, coders/decoders as well as flip-flops and derived building blocks such as shift-registers, counters, and general memory devices. Subsequently, they learn about the basics of processor and systems architecture, including elementary training in FPGA-based hardware design using vendor-specific design environments as well as an introduction to essential design suites exemplarily demonstrated by the Cadence tool suite.


Institut für Technische Informatik

Prof. Dr. Ing. Mladen Berekovic

Resp. Engineer: Christopher Blochwitz

Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134