Staff

Christopher Blochwitz, M. Sc.

Photo of Christopher  Blochwitz

Research Assistant


Ratzeburger Allee 160
23562 Lübeck
Building 64, Room 112 (2nd Floor)

Email:blochwitz(at)iti.uni-luebeck.de
Phone:+49 451 3101 6306
Fax:+49 451 3101 6304

Publications

[BKJ17] Blochwitz, C.; Klink, R.; Joseph, J. M.; Pionteck, T.: Contentious Live-Tracing as Debugging Approach on FPGAs. To Appear: ReConFig 2017, IEEE, Cancun, Mexiko 2017
[BWJ17] Blochwitz, C.; Wolff, J.; Joseph, J. M.; Werner, S.; Heinrich, D.; Groppe, S.; Pionteck, T.: Hardware-accelerated Radix-Tree based string sorting for Big Data applications. 30TH INTERNATIONAL CONFERENCE ON ARCHITECTURE OF COMPUTING SYSTEMS, Wien, 47-58, Springer, Cham 2017 [Paper]
[JBT17] Joseph, J.M; Blochwitz, C.; García-Ortiz, A.; Pionteck, T.: Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs. MICPRO 2460, 36–47, Elsevier, Amsterdam 2017 [Paper]
[GHB16] Groppe, S.; Heinrich, D.; Blochwitz, C.; Pionteck, T.: Constructing Large-Scale Semantic Web Indices for the Six RDF Collation Orders. Open Journal of Big Data (OJBD), 2016 [Paper]
[JBP16] Joseph, J.M.; Blochwitz, C.; Pionteck, T.: Adaptive Allocation of Default Router Paths in Network-on-Chips for Latency Reduction. 2016 International Conference on High Performance Computing & Simulation (HPCS) , Innsbruck 2016 [Paper]
[JWB16] Joseph, J. M.; Wrieden, S.; Blochwitz, C.; García-Ortiz, A.; Pionteck, T.: A Simulation Environment for Design Space Exploration for Asymmetric 3D-Network-on-Chip. 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), Tallinn 2016 [Paper]
[JWE16] Joseph, J. M.; Winker, T.; Ehlers, K.; Blochwitz, C.; Pionteck, T.: Hardware-Accelerated Pose Estimation for Embedded Systems using Vivado HLS . ReConFig, Cancun, Mexiko 2016 [Paper]
[WHG16] Werner, S.; Heinrich, D.; Groppe, S.; Blochwitz, C.; Pionteck, T.: Runtime Adaptive Hybrid Query Engine based on FPGAs. Open Journal of Databases (OJDB), 2016 [Paper]
[BJP15] Blochwitz, C.; Joseph, J. M.; Pionteck, T.; Backasch, R.; Werner, S.; Heinrich, D.; Groppen, S.: An optimized Radix-Tree for hardware-accelerated index generation for Semantic Web Databases. To Appear: International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexiko 2015
[GHW15] Groppe, S.; Heinrich, D.; Werner, S.; Blochwitz, C.; Pionteck, T.: PatTrieSort - External String Sorting based on Patricia Tries . Open Journal of Databases (OJDB), 2015 [Paper]
[HWS15] Heinrich, D.; Werner, S.; Stelzner, M.; Blochwitz, C.; Pionteck, T.; Groppe, S.: Hybrid FPGA Approach for a B+ Tree in a Semantic Web Database System. To Appear: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), IEEE, Bremen 2015
[JBP15] Joseph, J. M.; Blochwitz, C.; Pionteck, T.; Garcia-Ortiz, A.: Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs. Nordic Circuits and Systems Conference (NORCAS), IEEE, Oslo 2015
[WHP15] Werner, S.; Heinrich, D.; Piper, J.; Groppe, S.; Backasch, R.; Blochwitz, C.; Pionteck, T.: Automated Composition and Execution of Hardware-accelerated Operator Graphs. To Appear: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), IEEE, Bremen 2015
[JME17] Joseph, J. M.; Mey, M.; Ehlers, K.;Blochwitz, C.; Winker, T.; Pionteck, T.: Design Space Exploration for a Hardware-accelerated Embedded Real-Time Pose Estimation using Vivado HLS.